mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 13:04:28 +00:00
9471dcd296
Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
78 lines
2.5 KiB
Systemverilog
78 lines
2.5 KiB
Systemverilog
///////////////////////////////////////////
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// wallywrapper.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Wrapper module to define parameters for Wally Verilator linting
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "config.vh"
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import cvw::*;
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module wallywrapper;
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`include "parameter-defs.vh"
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logic clk;
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logic reset_ext, reset;
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logic [P.AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [P.PA_BITS-1:0] HADDR;
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logic [P.AHBW-1:0] HWDATA;
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logic [P.XLEN/8-1:0] HWSTRB;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
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logic UARTSin, UARTSout;
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logic SPIIn, SPIOut;
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logic [3:0] SPICS;
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logic SDCIntr;
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logic HREADY;
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logic HSELEXT;
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logic HSELEXTSDC;
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logic ExternalStall;
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// instantiate device to be tested
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assign GPIOIN = 0;
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assign UARTSin = 1;
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assign HREADYEXT = 1;
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assign HRESPEXT = 0;
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assign HRDATAEXT = 0;
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assign ExternalStall = '0;
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wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .ExternalStall, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HSELEXTSDC,
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.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
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.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
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.UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SDCIntr);
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endmodule
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