8 Commits

Author	SHA1	Message	Date
Rose Thompson	9471dcd296	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes. ... Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.	2024-07-19 17:08:47 -05:00
Rose Thompson	1f7d732dca	Moved the rvvisynth code to testbench since I only want this for simulation and fpga.	2024-05-24 16:10:58 -05:00
David Harris	568aa3c4a6	Verilator improvements	2023-11-04 03:21:07 -07:00
naichewa	e3d8162279	harris code review 3	2023-11-01 10:14:15 -07:00
Ross Thompson	a89a1e675c	Merge branch 'boot' into mergeBoot ... Merges Jacob's new sdc controller into wally.	2023-07-21 17:43:45 -05:00
Ross Thompson	443c568994	Vivado requires an intermediate wrapper file for parameterization.	2023-06-16 16:30:14 -05:00
Ross Thompson	75b5c23edd	Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems.	2023-06-15 14:05:44 -05:00
Ross Thompson	3ef2031791	Created temporary wrapper for lint.	2023-06-12 11:49:51 -05:00