Corey Hickson b1f340ba5c formatting		2024-10-30 03:39:55 -07:00
..
cache	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
ebu	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
fpu	formatting	2024-10-30 03:39:55 -07:00
generic	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
hazard	Merge branch 'rvvi'	2024-07-22 12:01:01 -05:00
ieu	Remove outdated code	2024-09-23 06:06:26 -07:00
ifu	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
lsu	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
mdu	Unused signal cleanup	2024-06-18 08:15:48 -07:00
mmu	Revert "This is a better solution. It's closer to the original book HPTW FSM,"	2024-10-11 17:02:51 -05:00
privileged	Implemented mhpmevent[3:31] as read-only zero rather than illegal	2024-10-15 09:08:25 -07:00
rvvi	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
uncore	Added wally header to spi_controller.	2024-10-29 10:53:33 -05:00
wally	Merge branch 'main' of github.com:openhwgroup/cvw into spiboot	2024-08-06 17:09:39 -05:00
cvw.sv	Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.	2024-07-24 12:47:50 -05:00