Rose Thompson eed6f11df6 Merge branch 'main' of github.com:ross144/cvw		2023-11-20 11:29:45 -06:00
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cache	Finally have the cbo way muxing controls reduced to something sane.	2023-11-20 11:28:03 -06:00
ebu	Merge branch 'main' into Zicclsm	2023-11-02 12:55:51 -05:00
fpu	Removed assign statement inside always block	2023-11-13 07:23:15 -08:00
generic	Commented IROM preloading	2023-11-19 19:33:57 -08:00
hazard	Fixed messed-up hazard.sv	2023-11-15 08:05:41 -08:00
ieu	turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep	2023-11-17 20:25:24 -08:00
ifu	Commented IROM preloading	2023-11-19 19:33:57 -08:00
lsu	Merge pull request #489 from ross144/main	2023-11-18 19:22:33 -08:00
mdu	turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep	2023-11-17 20:25:24 -08:00
mmu	Merge branch 'main' into Zicclsm	2023-11-10 16:15:32 -06:00
privileged	Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.	2023-10-30 09:56:17 -07:00
uncore	Merge branch 'spi' into main	2023-11-14 14:51:06 -08:00
wally	Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e	2023-11-14 11:01:58 -08:00
cvw.sv	Merge pull request #472 from ross144/main	2023-11-14 08:34:06 -08:00