Rose Thompson 438451ee02 Fixed the AMO hazard.		2023-12-15 11:55:54 -06:00
..
bmu	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-06-15 15:38:38 -05:00
alu.sv	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
comparator.sv	Found a whole bunch of files still using the old `define configurations.	2023-06-15 13:09:07 -05:00
controller.sv	Fixed the AMO hazard.	2023-12-15 11:55:54 -06:00
datapath.sv	turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep	2023-11-17 20:25:24 -08:00
extend.sv	Fixed cbo instruction decode.	2023-08-18 11:32:30 -05:00
forward.sv	More parameterization. Copied Lim. Still no slow down.	2023-05-24 14:49:22 -05:00
ieu.sv	On the way to solving the store delay hazard.	2023-12-13 10:39:01 -06:00
regfile.sv	Update regfile.sv	2023-06-12 12:21:25 -07:00
shifter.sv	Merge branch 'testbench-params2'	2023-06-15 15:31:13 -05:00