Ross Thompson c3b77926d5 I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.		2022-12-18 18:30:35 -06:00
..
slack-notifier	added instructions to slack notifier	2022-05-18 16:50:31 -07:00
wave-dos	Added generate around uncore.	2022-08-25 10:35:24 -05:00
buildrootBugFinder.py	update to match new filesystem organization	2022-03-26 21:28:32 +00:00
fpga-wave.do	Renamed signals in the cache.	2022-11-29 10:52:40 -06:00
lint-wally	Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width	2022-10-10 09:10:55 -07:00
linux-wave.do	Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.	2022-12-17 23:47:49 -06:00
make-tests.sh	simplified make-tests.sh to run the current makefile in regression	2022-05-17 17:29:34 -07:00
Makefile	More riscof makefile tuning	2022-07-25 21:15:56 +00:00
makefile-memfile	plic-s debug	2022-08-03 12:33:09 +00:00
regression-wally	Fixed regression-wally to correct remove and mkdir wkdir.	2022-12-16 12:51:21 -06:00
sim-buildroot	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
sim-buildroot-batch	sim-buildroot-batch now runs wally-pipelined-batch	2022-07-06 18:06:43 -07:00
sim-testfloat	Running 16-bit square root cases first in testfloat	2022-09-07 11:11:35 -07:00
sim-testfloat-batch	fixed error in divsqrt	2022-07-14 18:16:00 +00:00
sim-wally	FPU test list	2022-12-01 10:18:36 -08:00
sim-wally-batch	Renamed endianswap to match module name	2022-10-04 17:33:49 +00:00
testfloat.do	Moved fpu modules into subdirectories	2022-09-20 04:12:05 -07:00
wally-harvard.do	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00
wally-pipelined-batch.do	Reverted the IROM/DTIM address range modelsim assignment.	2022-11-30 17:13:33 -06:00
wally-pipelined.do	Updated tests for fpga and BP.	2022-12-18 16:24:26 -06:00
wave-all.do	Renamed signals in the cache.	2022-11-29 10:52:40 -06:00
wave-fpu.do	Updated testbench/wave for fdivsqrt new start signals	2022-11-22 22:22:26 +00:00
wave.do	I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.	2022-12-18 18:30:35 -06:00