Ross Thompson
c3b77926d5
I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
2022-12-18 18:30:35 -06:00
Ross Thompson
9d1cb9337e
Updated tests for fpga and BP.
2022-12-18 16:24:26 -06:00
Ross Thompson
5acdf541b9
Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.
2022-12-17 23:47:49 -06:00
Ross Thompson
9849983348
At long last found the subtle bug in the LRU.
...
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
2022-12-17 10:03:08 -06:00
Ross Thompson
3132246a46
Oups found a bug with the new flush cache states.
2022-12-16 16:22:40 -06:00
Ross Thompson
91e64a0d67
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
f04ca5cb6a
Fixed regression-wally to correct remove and mkdir wkdir.
2022-12-16 12:51:21 -06:00
David Harris
a8126458f6
Refactored stalls and flushes, including FDIV flush with FlushE
2022-12-15 10:56:18 -08:00
David Harris
97a432570a
Regression delete wkdir files to prevent spurious failures
2022-12-15 10:24:58 -08:00
David Harris
3a8602523e
FPU test list
2022-12-01 10:18:36 -08:00
Ross Thompson
fa22484cfe
Reverted the IROM/DTIM address range modelsim assignment.
2022-11-30 17:13:33 -06:00
Ross Thompson
2f582cd91f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-30 13:30:37 -06:00
Ross Thompson
de538d1c2f
Intermediate commit. Replaced flip flop dirty bit array with sram.
2022-11-30 00:08:31 -06:00
cturek
10c2d45888
div tests in sim-wally
2022-11-30 02:32:04 +00:00
Ross Thompson
fbf543bf57
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
2022-11-29 17:19:31 -06:00
Ross Thompson
96cc4c7ebe
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
2022-11-29 14:09:48 -06:00
Ross Thompson
78acd40424
Renamed signals in the cache.
2022-11-29 10:52:40 -06:00
Ross Thompson
6dd5668d21
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-22 18:07:32 -06:00
cturek
78c2ce5649
Updated testbench/wave for fdivsqrt new start signals
2022-11-22 22:22:26 +00:00
Ross Thompson
4e926ba4cf
Signal name changes for LRU.
2022-11-20 22:31:36 -06:00
Ross Thompson
13e6f7d80b
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
Ross Thompson
788ae5fb18
Updated wave file.
2022-11-13 21:34:45 -06:00
Ross Thompson
d912981ec9
Wavefile update.
2022-11-10 15:48:06 -06:00
Ross Thompson
51408c620e
Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
2022-10-23 13:46:50 -05:00
Ross Thompson
d6f907f444
Sort of solved the bit width warning for dtim, irom ranges.
2022-10-19 10:42:19 -05:00
David Harris
aa5fe52407
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-14 17:33:36 -07:00
David Harris
51b702fa17
Removed unused FPU waves
2022-10-14 17:33:32 -07:00
Ross Thompson
22603464ae
Fixed uncached read bug introduced by yesterday's changes.
2022-10-13 11:11:36 -05:00
Ross Thompson
dfd07a57fd
Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
...
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
2022-10-11 10:47:13 -05:00
David Harris
cc9a2fc62d
Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU
2022-10-10 10:22:12 -07:00
David Harris
31e9af0eb2
Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
2022-10-10 09:10:55 -07:00
Ross Thompson
9d23b0e6d6
Reorganized the configs.
2022-10-09 16:46:48 -05:00
Ross Thompson
b01ee070bd
Updated wavefile.
2022-10-05 14:55:40 -05:00
Kip Macsai-Goren
9a0b98037b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-10-04 17:33:54 +00:00
Kip Macsai-Goren
fb464b9546
Renamed endianswap to match module name
2022-10-04 17:33:49 +00:00
Ross Thompson
2c0132aa9c
Renamed signals in EBU.
2022-09-29 18:29:38 -05:00
David Harris
46680b80a7
Eliminated store after store stall when no cache; simplified divshiftcalc logic.
2022-09-21 13:02:34 -07:00
Ross Thompson
ac864a6ca3
Merged together bram1p1rw with sram1p1rw as sram1p1rw.
...
Fixed a major issue with the real SRAM implemenation.
2022-09-21 12:20:00 -05:00
David Harris
653c458241
Moved fpu modules into subdirectories
2022-09-20 04:12:05 -07:00
David Harris
59b6346a28
Removed unused otfc for Q
2022-09-19 00:43:27 -07:00
Ross Thompson
cea012a640
renamed multimanager to multicontroller.
2022-09-14 14:03:37 -05:00
Ross Thompson
c7d3580637
Renamed signals in the LSU.
2022-09-13 11:47:39 -05:00
David Harris
c730ddf74a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-07 11:11:39 -07:00
David Harris
7a29f9c95b
Running 16-bit square root cases first in testfloat
2022-09-07 11:11:35 -07:00
Ross Thompson
0615798467
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-07 12:26:50 -05:00
Ross Thompson
83306ec238
Named change for ahb tests to be less annoying.
2022-09-07 12:24:41 -05:00
Ross Thompson
3571fb18c2
Modified regression tests to add some ahb configurations.
2022-09-07 12:03:58 -05:00
David Harris
dff9416a33
Added rv32i config for regression of wally32periph
2022-09-07 09:37:59 -07:00
Ross Thompson
5a0cda9860
Merge branch 'multimanager' into main
2022-09-07 10:54:27 -05:00
David Harris
19e449b83d
Fixed regression for divsqrt radix2
2022-09-07 06:12:23 -07:00
