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https://github.com/openhwgroup/cvw
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107 lines
3.8 KiB
Systemverilog
107 lines
3.8 KiB
Systemverilog
///////////////////////////////////////////
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// ram.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: On-chip RAM, external to core
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// True-Dual-Port BRAM with Byte-wide Write Enable
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// Read-First mode
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// bytewrite_tdp_ram_rf.v
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//
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`include "wally-config.vh"
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module ram #(parameter BASE=0, RANGE = 65535) (
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input logic HCLK, HRESETn,
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input logic HSELRam,
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input logic [31:0] HADDR,
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input logic HWRITE,
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input logic HREADY,
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input logic [1:0] HTRANS,
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input logic [`XLEN-1:0] HWDATA,
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input logic [3:0] HSIZED,
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output logic [`XLEN-1:0] HREADRam,
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output logic HRESPRam, HREADYRam
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);
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logic [`XLEN/8-1:0] ByteMaskM;
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logic [31:0] HWADDR, A;
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logic prevHREADYRam, risingHREADYRam;
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logic initTrans;
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logic memwrite;
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logic [3:0] busycount;
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swbytemask swbytemask(.HSIZED, .HADDRD(HWADDR[2:0]), .ByteMask(ByteMaskM));
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assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
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// *** this seems like a weird way to use reset
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flopenr #(1) memwritereg(HCLK, 1'b0, initTrans | ~HRESETn, HSELRam & HWRITE, memwrite);
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flopenr #(32) haddrreg(HCLK, 1'b0, initTrans | ~HRESETn, HADDR, A);
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// busy FSM to extend READY signal
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always @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) begin
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busycount <= 0;
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HREADYRam <= #1 0;
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end else begin
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if (initTrans) begin
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busycount <= 0;
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HREADYRam <= #1 0;
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end else if (~HREADYRam) begin
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if (busycount == 0) begin // Ram latency, for testing purposes. *** test with different values such as 2
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HREADYRam <= #1 1;
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end else begin
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busycount <= busycount + 1;
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end
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end
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end
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assign HRESPRam = 0; // OK
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localparam ADDR_WDITH = $clog2(RANGE/8);
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localparam OFFSET = $clog2(`XLEN/8);
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// Rising HREADY edge detector
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// Indicates when ram is finishing up
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// Needed because HREADY may go high for other reasons,
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// and we only want to write data when finishing up.
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flopenr #(1) prevhreadyRamreg(HCLK,~HRESETn, 1'b1, HREADYRam,prevHREADYRam);
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assign risingHREADYRam = HREADYRam & ~prevHREADYRam;
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always @(posedge HCLK)
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HWADDR <= #1 A;
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bram2p1r1w #(`XLEN/8, 8, ADDR_WDITH)
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memory(.clk(HCLK), .enaA(1'b1),
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.addrA(A[ADDR_WDITH+OFFSET-1:OFFSET]), .doutA(HREADRam),
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.enaB(memwrite & risingHREADYRam), .weB(ByteMaskM),
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.addrB(HWADDR[ADDR_WDITH+OFFSET-1:OFFSET]), .dinB(HWDATA));
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endmodule
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