bbracker 11cf251378 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main		2021-04-15 21:09:27 -04:00
..
cache	Various code syntax changes to bring HDL to a synthesizable level	2021-04-13 11:27:12 -05:00
dmem	Implement support for superpages	2021-04-08 02:44:59 -04:00
ebu	working GPIO interrupt demo	2021-04-15 21:09:15 -04:00
fpu	integraded the FMA into the FPU	2021-04-15 18:28:00 +00:00
generic	change flop in ahb controller to use normal flop module	2021-03-10 19:14:02 +00:00
hazard	Partial fix to the integer divide stall issue.	2021-04-02 15:32:15 -05:00
ieu	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
ifu	Connect tlb and icache properly	2021-04-15 14:48:39 -04:00
mmu	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-04-15 16:20:43 -04:00
muldiv	Various code syntax changes to bring HDL to a synthesizable level	2021-04-13 11:27:12 -05:00
privileged	Add tests for scause and ucause	2021-04-15 19:41:25 -04:00
uncore	working GPIO interrupt demo	2021-04-15 21:09:15 -04:00
wally	Remove imem from testbenches	2021-04-14 20:20:34 -04:00