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Author	SHA1	Message	Date
Ross Thompson	dc97ee5f82	Have some sample code which I know works transmisting a packet.	2024-07-02 09:12:34 -07:00
David Harris	38b0c10f9b	Updated wallyTracer to be compatible with VCS	2024-07-02 04:47:53 -07:00
Jordan Carlin	2b4f12916e	Merge pull request #858 from davidharrishmc/dev ... Regression Improvements	2024-07-01 20:04:31 -07:00
Kevin Kim	ec4d4e2a8b	param defs lint	2024-06-30 19:15:42 -07:00
David Harris	68a105d5d8	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-06-29 05:35:46 -07:00
Kevin Kim	b04d387e7c	removed redundant signals	2024-06-28 22:13:35 -07:00
Kevin Kim	6cb6ff429b	Revert "intdivble changes" ... This reverts commit 3618c6c593.	2024-06-28 21:28:09 -07:00
Kevin Kim	3618c6c593	intdivble changes	2024-06-28 21:19:10 -07:00
Jordan Carlin	b0f5fbe497	Merge pull request #861 from stineje/main ... Temporarily removing Q tests as not everyone has tests	2024-06-28 12:54:18 -07:00
James Stine	f660779ba9	Fix for Q causing it to error out - commented out line for ISA and reset-val so can be put back	2024-06-28 12:17:15 -05:00
James Stine	8bb08fefe7	add three programs to APT to make sure they are there for new installs	2024-06-28 12:16:08 -05:00
David Harris	c972a914c8	Removed +plusarg_save because it doesn't silence VCS	2024-06-28 07:48:01 -07:00
David Harris	4a3532bf5a	VCS lockstep progress	2024-06-28 07:19:03 -07:00
David Harris	6cf250821d	Added VCS +plusarg_save to silence compiler	2024-06-28 06:53:44 -07:00
David Harris	e795143983	Turned off debug access to speed up VCS	2024-06-28 06:43:14 -07:00
David Harris	29c94e8abb	Regression fully running with Verilator, which is now the default and much faster than the others	2024-06-28 06:17:40 -07:00
David Harris	31b54fb247	Progress on VCS lockstep	2024-06-27 11:16:17 -07:00
David Harris	d933c80c55	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-06-27 07:07:08 -07:00
David Harris	4d87de2600	Merge pull request #855 from jordancarlin/derivgen_fix ... FPU without privilege modes + derived config fixes	2024-06-27 07:06:33 -07:00
Jordan Carlin	e7d4a2ee81	Trim down no priv regression tests	2024-06-27 07:01:55 -07:00
David Harris	bf9fdcf9f9	Cleaned up lint errors in testbench_fp; still not working in Verilator because readvectors receives the wrong unit, fmt, opctrl	2024-06-27 04:26:56 -07:00
David Harris	f12cdf55fe	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-06-27 03:22:55 -07:00
David Harris	2845d7eab1	Merge pull request #856 from jordancarlin/testbench_cleanup ... Testbench cleanup	2024-06-27 03:21:53 -07:00
Jordan Carlin	784151e165	Fix testbench_fp to use F_SUPPORTED, not S_SUPPORTED	2024-06-26 22:29:00 -07:00
Jordan Carlin	032de34dbd	Lint fixes for no priv mode configs	2024-06-26 22:15:18 -07:00
Jordan Carlin	47e67e99ff	Add no priv mode tests to regression	2024-06-26 22:00:29 -07:00
Jordan Carlin	c3cb4e5d1c	Fix FPU without S_SUPPORTED - #840	2024-06-26 22:00:29 -07:00
Jordan Carlin	607a09ca62	Add derived configs without privilege modes	2024-06-26 21:59:53 -07:00
Jordan Carlin	d3bb39d918	Fix derived configs with D_SUPPORTED = 0	2024-06-26 21:25:59 -07:00
Jordan Carlin	221f710baf	Use QUESTA as flag for	2024-06-26 21:18:40 -07:00
Ross Thompson	ccf4bb8ddc	Maybe have the incircuit trigger working.	2024-06-26 16:15:46 -07:00
David Harris	8fe2052b1f	Fix derived configuration with new derivgen script	2024-06-26 16:09:59 -07:00
David Harris	21e5fa3103	Merge pull request #854 from Shreesh-Kulkarni/main ... Files for Quad Precision Testing Support for Wally	2024-06-26 11:41:26 -07:00
Shreesh-Kulkarni	93fb0f2a84	Files for Quad Precision Testing Support for Wally	2024-06-26 11:36:04 -07:00
Ross Thompson	612a281f62	Added module to receive ethernet frame and trigger the ila.	2024-06-26 11:05:31 -07:00
David Harris	a013c7083f	Merge pull request #853 from jordancarlin/derivgen_fix ... Fix derivgen	2024-06-26 08:31:22 -07:00
Jordan Carlin	1a1da9b2c4	Update derivlist.txt based on exact matching	2024-06-26 07:49:27 -07:00
Jordan Carlin	0da6e35988	Fix derivgen.pl to find exact keys	2024-06-26 07:45:04 -07:00
Jordan Carlin	f003f8fae9	Merge pull request #852 from davidharrishmc/dev ... Clean up unused signals for derived configurations	2024-06-26 07:34:00 -07:00
David Harris	0fcc7878dc	Updated march lists	2024-06-25 21:54:58 -07:00
Ross Thompson	74189e1e4b	Have vivado triggering the ILA after the mismatch but the latency is way too long.	2024-06-25 17:04:14 -07:00
Ross Thompson	fa26c9a8b5	Added pipe to vivado to create ila trigger from rvvidaemon.	2024-06-25 13:07:46 -07:00
Kevin Kim	eeea783da0	lint	2024-06-21 23:15:34 -07:00
Kevin Kim	4877633977	lint fixes tests vh	2024-06-21 22:16:09 -07:00
Kevin Kim	19f0cf7a35	putting back tests in tests vh	2024-06-21 21:51:44 -07:00
Kevin Kim	e6dc50308a	integer postprocessing hardware matches diagram	2024-06-21 21:50:55 -07:00
Kevin Kim	00bf3faa9c	changed intdivb width	2024-06-21 21:31:19 -07:00
Jordan Carlin	b76941d278	Use VCS built-in default macro instead of defining SIM_VCS	2024-06-21 15:17:59 -07:00
Kevin Kim	9a59c8e07f	reduced bit widths for integer on fpu	2024-06-20 23:46:45 -07:00
Ross Thompson	249d58244a	It's working!!!!!!	2024-06-20 15:48:30 -07:00