Rose Thompson
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f8b65f50b0
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Fixed bugs in the updated fpga synthe script.
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2023-11-13 18:10:22 -06:00 |
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Rose Thompson
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d5f0c15b90
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Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.
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2023-11-13 17:48:28 -06:00 |
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Rose Thompson
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95fc5f4a1c
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Towards removing the FPGA config file.
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2023-11-13 17:20:26 -06:00 |
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Rose Thompson
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6b7ff50a84
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Reduced Arty A7 clock speed to 20Mhz to support Zicclsm.
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2023-11-13 16:44:02 -06:00 |
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Rose Thompson
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a6995af91c
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Fixed bug in uncore updates which broke SDC.
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2023-11-13 16:15:23 -06:00 |
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Rose Thompson
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707b0c557c
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Cleanup and optimization of Zicclsm.
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2023-11-13 14:28:22 -06:00 |
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Rose Thompson
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da59cb71a9
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Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config.
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2023-11-13 14:12:27 -06:00 |
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Rose Thompson
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540d8d930d
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Cleanup.
Linux makefile
wally tracer. probably reduce some complexity here.
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2023-11-13 14:04:43 -06:00 |
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Rose Thompson
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1f7d91e8e0
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Merge branch 'Zicclsm'
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2023-11-13 13:53:42 -06:00 |
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Rose Thompson
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55bcc4dbc1
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Updates to linux config files for sdc.
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2023-11-13 13:53:23 -06:00 |
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Rose Thompson
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13908ac41c
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Updated buildroot to use kernel 6.6 and added dedicated qemu emulation script.
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2023-11-13 12:36:32 -06:00 |
|
Rose Thompson
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cc7a0b211a
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Cleanup.
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2023-11-13 12:35:11 -06:00 |
|
Rose Thompson
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c8cca8dfb8
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Simplification.
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2023-11-10 18:39:36 -06:00 |
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Rose Thompson
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9dfe421c55
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Yay! Zicclsm passes my regression test now.
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2023-11-10 18:28:51 -06:00 |
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Rose Thompson
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c0e02ae190
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Found another bug in the RTL's Zicclsm alignment.
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2023-11-10 18:26:55 -06:00 |
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Rose Thompson
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02ab9fe99c
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Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.
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2023-11-10 17:58:42 -06:00 |
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Rose Thompson
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bd866e1025
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Fixed some more bugs in the Zicclsm signature.
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2023-11-10 17:36:10 -06:00 |
|
Rose Thompson
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efecb0c346
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Fixed bug in the Zicclsm test.
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2023-11-10 17:34:23 -06:00 |
|
Rose Thompson
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84d86b1994
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Fixed spill bugs in the aligner.
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2023-11-10 17:18:45 -06:00 |
|
Rose Thompson
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ada354f443
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Fixed bug in the misaligned access test.
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2023-11-10 17:02:15 -06:00 |
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Rose Thompson
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b74bfbeefd
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Merge branch 'main' into Zicclsm
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2023-11-10 16:15:32 -06:00 |
|
Rose Thompson
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baacb6f6eb
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Missed tests.vh.
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2023-11-10 16:10:10 -06:00 |
|
Rose Thompson
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9abd26aad9
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Fixed bug which broke the non Zicclsm configs.
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2023-11-10 16:08:04 -06:00 |
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Rose Thompson
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e1a7c7986a
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Merge pull request #463 from davidharrishmc/dev
Dev
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2023-11-10 08:48:07 -08:00 |
|
David Harris
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426aabbc1a
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Imperas commenting
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2023-11-10 08:26:32 -08:00 |
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David Harris
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7e00581187
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Add Svadu support and SPI to imperas configuration
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2023-11-10 06:27:25 -08:00 |
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David Harris
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d7ced56c60
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Merge pull request #460 from naichewa/main
removed vestigial logic, added comments, deleted unused signals
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2023-11-10 05:18:57 -08:00 |
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naichewa
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5ce16dcb63
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Cleanup
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2023-11-09 16:52:55 -08:00 |
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naichewa
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3052a68d84
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Remove old 2/4 bit logic, add comments,
clean up unused signals
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2023-11-09 16:48:11 -08:00 |
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David Harris
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bae3772548
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-09 10:33:25 -08:00 |
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Rose Thompson
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1d2eccc14d
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Merge pull request #458 from stineje/main
fix to setup.csh and also ppaSynth.py
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2023-11-09 10:20:05 -08:00 |
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David Harris
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625652b9ca
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Reporting stall path in synthesis script, support Zcb in Imperas
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2023-11-09 06:59:29 -08:00 |
|
James E. Stine
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9a47667fd7
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update README on ppa
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2023-11-09 01:00:33 -06:00 |
|
James E. Stine
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5a115bc6f2
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update ppaSynth.py with runCommand
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2023-11-09 00:52:40 -06:00 |
|
James E. Stine
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a6bc69d73f
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Add encoding for utf-8 on wrapperGen.py to avoid issue with incorrect encoding on RHEL C-shell
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2023-11-08 23:57:59 -06:00 |
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David Harris
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32f68ac4e5
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-08 16:06:50 -08:00 |
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David Harris
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0e1b4bf8f6
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Merge pull request #459 from naichewa/main
hardware interlock and hold mode fixes
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2023-11-08 16:06:39 -08:00 |
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naichewa
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b13b8feee4
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updated to-do comments
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2023-11-08 15:28:51 -08:00 |
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naichewa
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d67badfc60
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fix hardware interlock, hold mode deassert
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2023-11-08 15:20:51 -08:00 |
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James E. Stine
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41f4c634b0
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Update to ppaSynth and ppaAnalyze - still have to push in mod for ppaAnalyze to plot more refined plots as well as some other plots - I have a fix working - just need to push in which will do later today
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2023-11-08 14:00:36 -06:00 |
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James E. Stine
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f83188a4a4
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add typo on setting WALLY for C-shell that caused some incompatability issues
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2023-11-08 13:59:04 -06:00 |
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Rose Thompson
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44c60a3e76
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Merge pull request #455 from davidharrishmc/dev
Bit manipulation imperas config, fsqrt code changes to match chapter
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2023-11-08 08:27:15 -08:00 |
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David Harris
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89796c2dd7
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-08 02:55:00 -08:00 |
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David Harris
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b1994f12fa
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Merge pull request #456 from naichewa/main
fifo fixes and edge case testing
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2023-11-08 02:54:06 -08:00 |
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naichewa
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a5837eb62c
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fifo fixes and edge case testing
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2023-11-07 17:59:46 -08:00 |
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David Harris
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637cc3b78a
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Reparitioned sign logic in fdivsqrt to match paper
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2023-11-06 14:11:42 -08:00 |
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David Harris
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2b183020d5
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Fixed bit manpulation on imperas config
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2023-11-06 14:11:01 -08:00 |
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Rose Thompson
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380694293f
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Merge pull request #453 from davidharrishmc/dev
Fixed regression error of watchdog timeout when PCM is optimized out of the IFU
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2023-11-05 15:53:57 -08:00 |
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David Harris
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bddd2d573e
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Shortened path to PCSrcE in logger to avoid problematic hierarchical reference
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2023-11-05 07:06:53 -08:00 |
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David Harris
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9c4a7866b8
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Fixed Svnapot_page_mask for imperas.ic
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2023-11-05 06:51:01 -08:00 |
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