11 Commits

Author	SHA1	Message	Date
Ross Thompson	85567841eb	Merge branch 'testbench-params2'	2023-06-15 15:31:13 -05:00
Ross Thompson	d2219023c3	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-06-15 14:57:23 -05:00
Harshini Srinath	dd7c13cc2d	Update wallypipelinedsoc.sv ... Program clean up	2023-06-15 10:39:37 -07:00
Ross Thompson	ee4352975c	This parameterizes the testbench but does not use the verilator updates or the new testbench.	2023-06-12 11:00:30 -05:00
Ross Thompson	1ceea51d8b	Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet.	2023-05-31 16:51:00 -05:00
Ross Thompson	a963f0af3a	Updated source code to be compatible with verilator 5.011 for lint only.	2023-05-31 10:44:23 -05:00
Ross Thompson	02a788a083	PMA checker's address decoder is now parameterized. I did not see bit slicing in Lim's code. I'm not sure how they got around this issue.	2023-05-26 11:06:48 -05:00
Ross Thompson	930fb67308	Trying to figure out why the parameterization slowed down modelsim so much.	2023-05-24 12:44:42 -05:00
Ross Thompson	0afba56927	Updated GPIO signal names to reflect book.	2023-03-24 18:55:43 -05:00
Ross Thompson	46b1bca4fc	Fixed all tap/space issue in RTL.	2023-03-24 17:32:25 -05:00
David Harris	78eb90715c	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00