David Harris
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a1eccf37dc
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Fix Issue 145
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2023-03-22 04:33:14 -07:00 |
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David Harris
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df9ce03252
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Renamed intdivrestoring to div
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2023-03-21 05:51:02 -07:00 |
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David Harris
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718844012e
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Renamed intdivrestoring to div
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2023-03-20 16:22:06 -07:00 |
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David Harris
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18737b58df
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formatting cleanup
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2023-03-20 12:45:10 -07:00 |
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David Harris
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cd0240d938
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Eliminate transitions to FLUSH and WRITEBACK in cachefsm for READ_ONLY_CACHE
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2023-03-19 10:41:47 -07:00 |
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David Harris
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4c6f539449
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Removed flq from LLEN=64
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2023-03-19 10:25:04 -07:00 |
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David Harris
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ff22520d9e
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Added comments about PMP checker fixes when test cases will be ready to initialize PMP before entering user mode
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2023-03-19 05:46:34 -07:00 |
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David Harris
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4cde207958
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Fix Issue #120 about SIE/SIP being 0 unless MIDELEG bits are set. However, this fix breaks the wally32/64priv tests in regression.
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2023-03-18 10:10:58 -07:00 |
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David Harris
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f53b2f6e1f
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-03-18 09:24:37 -07:00 |
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David Harris
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6922298f21
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Replaced FenceM with InvalidateICacheM for event counting of fence.i
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2023-03-18 09:24:31 -07:00 |
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Ross Thompson
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3d37d2769a
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Book updates.
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2023-03-14 13:09:50 -05:00 |
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Ross Thompson
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3cae6ca90f
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Updated NextAdr to NextSet.
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2023-03-13 14:54:13 -05:00 |
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Ross Thompson
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c190444fa2
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Updated CAdr to CacheSet.
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2023-03-13 14:53:00 -05:00 |
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Ross Thompson
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ada099c58b
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Changes BTA to BPBTA.
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2023-03-12 14:36:46 -05:00 |
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Ross Thompson
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a5523400ae
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Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10.
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2023-03-12 13:21:22 -05:00 |
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David Harris
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f411803bc4
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-03-10 12:47:30 -08:00 |
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David Harris
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33fa7e4706
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Simplified SLT and SLTU code in ALU
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2023-03-09 15:14:52 -08:00 |
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Ross Thompson
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68b437ce92
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-03-09 13:29:38 -06:00 |
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Ross Thompson
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4db17cde2f
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Updated testbench to record coremark performance counters.
Added comment about mtval probably not being correct for compressed instructions.
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2023-03-08 17:11:27 -06:00 |
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David Harris
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88c3a61cd7
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-03-07 14:49:23 -08:00 |
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kipmacsaigoren
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24f0f34aff
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Merge branch 'openhwgroup:main' into priv-tests
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2023-03-07 13:46:55 -08:00 |
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David Harris
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77ba71be71
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editorconfig to specify tabs/spaces. Fixed some tabs. Turn off coverage to speed up simulation
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2023-03-07 06:31:40 -08:00 |
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Ross Thompson
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6d4e28fdf2
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-03-06 22:29:27 -06:00 |
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Ross Thompson
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e448cd54ef
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-03-06 18:39:15 -06:00 |
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Ross Thompson
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a6b851a672
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Renamed signals to be consistent with textbook.
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2023-03-06 18:29:31 -06:00 |
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Ross Thompson
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31fcc0daf7
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Renamed PCFSpill to PCSpillF.
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2023-03-06 17:50:57 -06:00 |
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Ross Thompson
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473ed2b475
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Renamed InstrFirstHalf to InstrFirstHalfF.
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2023-03-06 17:48:57 -06:00 |
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Ross Thompson
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fdfb80a818
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Renamed ebuarbfsm to ebufsmarb to match figures.
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2023-03-06 17:47:55 -06:00 |
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David Harris
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7ecf4cdea8
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Fixed bug about rv64 shifts only using 6 bits of funct7
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2023-03-06 13:10:51 -08:00 |
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David Harris
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7e0c96cdcc
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Simplified decoder default to illegal instruction
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2023-03-06 11:21:11 -08:00 |
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David Harris
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c2efdbdbbb
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More detailed decoding of load/store/branch/jump
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2023-03-06 11:15:48 -08:00 |
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David Harris
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a56557d847
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Improved decoding illegal instructions in controller
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2023-03-06 11:02:42 -08:00 |
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Kip Macsai-Goren
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a38f7cc8a1
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added reset values to stime and stimecmp registers
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2023-03-04 15:06:15 -08:00 |
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Ross Thompson
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da74ed0369
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Merge pull request #126 from davidharrishmc/dev
ImperasDV setup
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2023-03-03 18:01:32 -06:00 |
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David Harris
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876c33da5f
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-03-03 15:54:42 -08:00 |
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Ross Thompson
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0cb5369351
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Renamed BTB misprediction to BTA.
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2023-03-03 00:18:34 -06:00 |
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Ross Thompson
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5b5677ccb8
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Added divide cycle counter.
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2023-03-02 23:59:52 -06:00 |
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Ross Thompson
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aabb454d1c
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Added the i and d cache cycle counters.
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2023-03-02 23:54:56 -06:00 |
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Ross Thompson
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cfca77172e
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Added fence counter.
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2023-03-02 23:29:20 -06:00 |
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Ross Thompson
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f32f8c109a
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Added csr write counter, sfence vma counter, interrupt counter, and exception counter.
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2023-03-02 23:21:29 -06:00 |
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Ross Thompson
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a313b10912
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Added store stall to performance counters.
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2023-03-02 23:10:54 -06:00 |
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Ross Thompson
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2dd693a3b3
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Reordered performance counters and added space for new ones.
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2023-03-02 23:04:31 -06:00 |
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David Harris
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316b8b2250
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Refactored Floating point division special case detection to avoid spurious trigger on Y for sqrt)
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2023-03-02 20:00:47 -08:00 |
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Ross Thompson
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b98e007a53
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Cleaned up branch predictor performance counters.
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2023-03-01 17:05:42 -06:00 |
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David Harris
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5c8c50adba
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-03-01 11:18:05 -08:00 |
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David Harris
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23775c6d67
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Renamed I/D TLBMissOrDAFault to TLBMissOrUpdateDA for consistency with UpdateDA
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2023-03-01 11:18:00 -08:00 |
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Ross Thompson
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90b2f0a652
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Set bp to use instruction class prediction by default.
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2023-03-01 11:52:42 -06:00 |
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Ross Thompson
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dea6b643a6
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Branch predictor cleanup.
I think Ch 10 is now done except for BTB performance analysis and the section on running benchmarks and collecting data.
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2023-03-01 11:24:24 -06:00 |
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Ross Thompson
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03a6679ba0
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More btb cleanup.
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2023-03-01 10:47:00 -06:00 |
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Ross Thompson
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554e7d0973
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Minor fix to btb.
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2023-03-01 10:45:40 -06:00 |
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