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Author	SHA1	Message	Date
David Harris	f64c0589fe	FPU test list	2022-12-01 10:18:36 -08:00
David Harris	558f0b655e	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-12-01 08:15:51 -08:00
David Harris	4e5f62a5c1	code cleanup	2022-12-01 08:15:48 -08:00
Ross Thompson	b0b16acaf5	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-30 17:19:04 -06:00
David Harris	aa26a97b36	signal sufixes in integer division	2022-11-30 15:15:37 -08:00
Ross Thompson	f9ffcf377b	Reverted the IROM/DTIM address range modelsim assignment.	2022-11-30 17:13:33 -06:00
Ross Thompson	bfd238a4fc	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-30 13:30:37 -06:00
Ross Thompson	813b2963fb	More optimization.	2022-11-30 11:26:48 -06:00
Ross Thompson	da7b13ba0a	Removed reset on dirty cache bits.	2022-11-30 11:04:37 -06:00
Ross Thompson	5e5cca6ae1	Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.	2022-11-30 11:01:25 -06:00
Ross Thompson	ac3e02692b	Preparing to merge dirty and tag srams.	2022-11-30 10:40:48 -06:00
Ross Thompson	8692ccbafb	Intermediate commit. Replaced flip flop dirty bit array with sram.	2022-11-30 00:08:31 -06:00
cturek	e28a6901a9	div tests in sim-wally	2022-11-30 02:32:04 +00:00
Ross Thompson	e3577781b0	Optimization of cacheway.	2022-11-29 18:30:47 -06:00
Ross Thompson	1e2180ef98	Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.	2022-11-29 17:19:31 -06:00
Ross Thompson	5e550fe5e6	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-29 14:57:38 -06:00
Ross Thompson	9e4166407b	Fixed a bug with the replacement policy. It was updating the wrong set on load hits.	2022-11-29 14:51:09 -06:00
Ross Thompson	179d321683	Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.	2022-11-29 14:09:48 -06:00
Kip Macsai-Goren	66fcb2bffe	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-29 10:43:44 -08:00
Kip Macsai-Goren	26b4147f40	added failing satp invalid tests to regression	2022-11-29 10:43:38 -08:00
Ross Thompson	34bff09721	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-29 11:52:35 -06:00
Ross Thompson	ed54959378	Renamed signals in the cache.	2022-11-29 10:52:40 -06:00
Kip Macsai-Goren	af00eadec2	added tests for invalid address being written to satp. Not passing regression	2022-11-27 13:22:35 -08:00
Ross Thompson	4e52755c9f	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-22 18:07:32 -06:00
cturek	7140642c93	Almost done with Int division	2022-11-22 22:22:59 +00:00
cturek	3fbccbf119	Updated testbench/wave for fdivsqrt new start signals	2022-11-22 22:22:26 +00:00
Ross Thompson	1736983557	Cleanup cacheLRU.	2022-11-22 14:59:01 -06:00
Ross Thompson	2ae7b555be	File name change for cachereplacement policy to cacheLRU	2022-11-20 22:35:02 -06:00
Ross Thompson	84679c0062	Signal name changes for LRU.	2022-11-20 22:31:36 -06:00
Ross Thompson	55335d1db6	Updated top level fpga file.	2022-11-18 11:10:45 -06:00
Ross Thompson	840517a582	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-17 17:45:59 -06:00
Ross Thompson	736a30afac	Missing a file. Last commit will fail.	2022-11-17 17:45:41 -06:00
Ross Thompson	4fbda554ee	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-17 17:38:52 -06:00
Ross Thompson	a1f39a8186	Finally have the correct replacement policy implementation.	2022-11-17 17:36:37 -06:00
Ross Thompson	8692bafd04	Updated fpga wave configuration.	2022-11-16 15:57:19 -06:00
Ross Thompson	b108e0a594	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-16 15:39:17 -06:00
Ross Thompson	ac0f6ddb7b	I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.	2022-11-16 15:38:37 -06:00
Ross Thompson	9b2236b2a0	Progress on the cache replacement policy implementation.	2022-11-16 15:35:34 -06:00
Ross Thompson	d1ce84d172	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-16 12:44:06 -06:00
Ross Thompson	cf964e30fb	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-16 12:42:29 -06:00
Ross Thompson	5f7b0b8a9b	Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.	2022-11-16 12:36:58 -06:00
David Harris	bc3b783543	comment cleanup	2022-11-16 10:23:20 -08:00
David Harris	ddba68605e	Renamed DivBusy to FDivBusyE in FPU	2022-11-16 10:13:27 -08:00
David Harris	e008d663f4	Moved DivStartE to fdivsqrtfsm	2022-11-16 10:00:07 -08:00
Ross Thompson	900a326a23	Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out.	2022-11-16 11:15:34 -06:00
Ross Thompson	3fbacc2339	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-15 14:49:32 -06:00
cturek	6fe35ee0e3	Attempt to fix FPGA synth errors	2022-11-15 20:34:28 +00:00
cturek	1c49d4a1c2	Fixed lint errors in postprocessing	2022-11-15 20:31:23 +00:00
Ross Thompson	3de5144ae4	Updated vcu118 constraints to run cpu at 38.43Mhz.	2022-11-15 10:19:38 -06:00
Ross Thompson	4b5ec21ef4	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-15 10:18:56 -06:00