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Attempt to fix FPGA synth errors

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cturek 2022-11-15 20:34:28 +00:00
parent 1c49d4a1c2
commit 6fe35ee0e3
1 changed files with 26 additions and 26 deletions
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52
pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -82,55 +82,55 @@ module fdivsqrtpostproc(
always_comb
if (~As)
if (NegSticky) begin
assign NormQuot = FirstUM;
assign NormRem = W + RemD;
assign PostInc = 0;
NormQuot = FirstUM;
NormRem = W + RemD;
PostInc = 0;
end else begin
assign NormQuot = FirstU;
assign NormRem = W;
assign PostInc = 0;
NormQuot = FirstU;
NormRem = W;
PostInc = 0;
end
else
if (NegSticky | weq0) begin
assign NormQuot = FirstU;
assign NormRem = W;
assign PostInc = 0;
NormQuot = FirstU;
NormRem = W;
PostInc = 0;
end else begin
assign NormQuot = FirstU;
assign NormRem = W - RemD;
assign PostInc = 1;
NormQuot = FirstU;
NormRem = W - RemD;
PostInc = 1;
end
/*
always_comb
if(ALTB) begin
assign IntQuot = '0;
assign IntRem = ForwardedSrcAE;
IntQuot = '0;
IntRem = ForwardedSrcAE;
end else if (BZero) begin
assign IntQuot = '1;
assign IntRem = ForwardedSrcAE;
IntQuot = '1;
IntRem = ForwardedSrcAE;
end else if (EarlyTerm) begin
if (weq0) begin
assign IntQuot = FirstU;
assign IntRem = '0;
IntQuot = FirstU;
IntRem = '0;
end else begin
assign IntQuot = FirstUM;
assign IntRem = '0;
IntQuot = FirstUM;
IntRem = '0;
end
end else begin
assign IntQuot = NormQuot;
assign IntRem = NormRem;
IntQuot = NormQuot;
IntRem = NormRem;
end
*/
/*
always_comb
if (RemOp) begin
assign NormShift = m + (`DIVBLEN)'(`DIVa);
assign PreResult = IntRem;
NormShift = m + (`DIVBLEN)'(`DIVa);
PreResult = IntRem;
end else begin
assign NormShift = DIVb - (j << `LOGR);
assign PreResult = IntQuot;
NormShift = DIVb - (j << `LOGR);
PreResult = IntQuot;
end
*/