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comment cleanup

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This commit is contained in:
David Harris 2022-11-16 10:23:20 -08:00
parent ddba68605e
commit bc3b783543
2 changed files with 3 additions and 3 deletions
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4
pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
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@ -61,8 +61,8 @@ module fdivsqrtfsm(
// *** start logic is presently in fctl. Make it look more like integer division start logic
// DivStartE comes from fctrl, reflecitng the start of floating-point and possibly integer division
assign DivStartE = (FDivStartE | IDivStartE) & (state == IDLE) & ~StallM;
assign DivDone = (state == DONE) | (WZero & (state == BUSY));
assign FDivBusyE = (state == BUSY & ~DivDone);
assign DivDone = (state == DONE) | (WZero & (state == BUSY)); // *** used in postprocess.sv and round.sv. This doesn't seem proper. They break when removed.
assign FDivBusyE = (state == BUSY & ~DivDone); // *** want to add | DivStartE but it creates comb loop
// Divider control signals from MDU
//assign DivBusyE = (state == BUSY) | DivStartE;

2
pipelined/src/fpu/postproc/postprocess.sv
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@ -129,7 +129,7 @@ module postprocess (
assign Mult = OpCtrl[2]&~OpCtrl[1]&~OpCtrl[0];
assign CvtOp = (PostProcSel == 2'b00);
assign FmaOp = (PostProcSel == 2'b10);
assign DivOp = (PostProcSel == 2'b01)&DivDone;
assign DivOp = (PostProcSel == 2'b01) & DivDone;
assign Sqrt = OpCtrl[0];
// is there an input of infinity or NaN being used