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f557150cae
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195 Commits

Author SHA1 Message Date
Ross Thompson
f557150cae Rename LineByteMux to FetchbufferbyteSel. 2022-12-04 01:00:04 -06:00
Ross Thompson
3442b04f9e Properly flush cacheLRU. 2022-12-01 17:32:58 -06:00
Ross Thompson
5025664cb0 Removed unused port on cacheway. 2022-12-01 11:47:48 -06:00
Ross Thompson
a6355b1dcb More optimization. 2022-11-30 11:26:48 -06:00
Ross Thompson
0aa7ce0b24 Removed reset on dirty cache bits. 2022-11-30 11:04:37 -06:00
Ross Thompson
cedb234013 Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now. 2022-11-30 11:01:25 -06:00
Ross Thompson
0454eb95ad Preparing to merge dirty and tag srams. 2022-11-30 10:40:48 -06:00
Ross Thompson
de538d1c2f Intermediate commit. Replaced flip flop dirty bit array with sram. 2022-11-30 00:08:31 -06:00
Ross Thompson
453ea36512 Optimization of cacheway. 2022-11-29 18:30:47 -06:00
Ross Thompson
b5718c9baa Fixed a bug with the replacement policy. It was updating the wrong set on load hits. 2022-11-29 14:51:09 -06:00
Ross Thompson
96cc4c7ebe Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled. 2022-11-29 14:09:48 -06:00
Ross Thompson
78acd40424 Renamed signals in the cache. 2022-11-29 10:52:40 -06:00
Ross Thompson
279f5bc615 Cleanup cacheLRU. 2022-11-22 14:59:01 -06:00
Ross Thompson
e1dbe58632 File name change for cachereplacement policy to cacheLRU 2022-11-20 22:35:02 -06:00
Ross Thompson
4e926ba4cf Signal name changes for LRU. 2022-11-20 22:31:36 -06:00
Ross Thompson
0106777f02 Finally have the correct replacement policy implementation. 2022-11-17 17:36:37 -06:00
Ross Thompson
22ad49eef2 Progress on the cache replacement policy implementation. 2022-11-16 15:35:34 -06:00
Ross Thompson
42111db671 Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr. 2022-11-16 12:36:58 -06:00
Ross Thompson
1f21a2bab1 Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out. 2022-11-16 11:15:34 -06:00
Ross Thompson
b53f8eceef Renamed Flush to FlushStage in the cache. 2022-11-14 14:11:05 -06:00
Ross Thompson
13e6f7d80b Changed names of cache signals. 2022-11-13 21:36:12 -06:00
Ross Thompson
8658a25218 Renamed Word to Beat for ahbcacheinterface. 2022-11-09 17:52:50 -06:00
Ross Thompson
be8e0eee1b Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU). 
FlushW prevents writting the cache, dtim, and bus state.  FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
 2022-11-07 15:50:55 -06:00
Ross Thompson
44171c342d Reduced complexity of logic supressing cache operations. 2022-11-01 15:23:24 -05:00
Ross Thompson
6696624971 comment updates. 2022-10-22 16:28:44 -05:00
Ross Thompson
2c5847b01f Moving interlockfsm changes to a temporary branch. 
reduced complexity of cache mux controls.
 2022-10-19 15:08:23 -05:00
Ross Thompson
494f8b94f4 Reordered the eviction and fetch in cache so it follows a more logical order. 2022-10-04 17:36:07 -05:00
Ross Thompson
18e739befc Modified cache lru to not have the delayed write. 2022-10-04 15:14:58 -05:00
Ross Thompson
4062fe56c0 Possible fix to the bus cache interaction. 2022-09-27 11:34:33 -05:00
Ross Thompson
07bb11518e Found a hidden bug in the cache to bus fsm interlock. 2022-09-26 17:41:30 -05:00
Ross Thompson
0fcc314d06 Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed. 2022-09-26 12:48:26 -05:00
Ross Thompson
38edbde966 Renamed RW signals through the caches, bus interfaces, and IFU/LSU. 
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
 2022-09-23 11:46:53 -05:00
Ross Thompson
cec50ce208 The valid and dirty bits match the SRAM implementation now. 2022-09-22 16:09:09 -05:00
Ross Thompson
b48d6b5e1f Solved the sram write first / read first issue. Works correctly with read first now. 2022-09-22 14:16:26 -05:00
Ross Thompson
3fb0a13fe2 Moved other SRAMs to generic/mem. 2022-09-21 12:36:03 -05:00
Ross Thompson
ac864a6ca3 Merged together bram1p1rw with sram1p1rw as sram1p1rw. 
Fixed a major issue with the real SRAM implemenation.
 2022-09-21 12:20:00 -05:00
Ross Thompson
c0884ecc63 Modified sram1p1rw to support 3 different implementation styles. 
SRAM, Read first, and Write first.
 2022-09-21 11:26:00 -05:00
Ross Thompson
2c86badeb2 pipelining of fetch into evict AHB requests. 2022-09-13 17:51:55 -05:00
Ross Thompson
7f1ae039b0 Optimization. Able to remove hptw address muxes from the E stage. 2022-09-08 15:51:18 -05:00
Ross Thompson
1b339f0547 Moved files around. 2022-08-31 14:08:06 -05:00
Ross Thompson
8156109add More cleanup. 2022-08-31 11:12:38 -05:00
Ross Thompson
4b167ad21e More simplifications. 2022-08-31 10:45:16 -05:00
Ross Thompson
a93c5b0f0a Trade off. Added additional state to bus fsm separating STATE_CACHE_ACCESS into STATE_CACHE_FETCH and STATE_CACHE_EVICT. This allows removing CacheRWDelay. Saves a bit of logic but fsm is more complex. Also the fsm outputs are simplier. 2022-08-31 10:36:30 -05:00
Ross Thompson
ed2a9225ea Removed unused old versions of the bus controllers. 2022-08-31 09:51:54 -05:00
Ross Thompson
89f13370e2 Removed old signals. 2022-08-31 09:50:39 -05:00
Ross Thompson
5409501ca6 Maybe fixed it? 2022-08-30 18:08:34 -05:00
Ross Thompson
8b9f30c91a more progress. 2022-08-30 17:32:32 -05:00
Ross Thompson
315f662eb9 More progress. 2022-08-30 15:27:19 -05:00
Ross Thompson
637d60b64c Progress. 2022-08-30 14:17:00 -05:00
Ross Thompson
8cf3c7b352 new cache bus fsm not working but lints. 
Forgot a few files in the last commit.
 2022-08-30 10:58:07 -05:00