243 Commits

Author	SHA1	Message	Date
David Harris	29f57958a9	Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match	2023-12-14 15:32:36 -08:00
David Harris	8eea2bdcc0	Merge pull request #531 from ross144/main ... Updated wavefile	2023-12-14 14:52:31 -08:00
Rose Thompson	bb712d6860	Updated wavefile.	2023-12-14 14:36:23 -06:00
Rose Thompson	53bf68a585	Merge pull request #528 from davidharrishmc/dev ... Svnapot bug fix	2023-12-13 21:30:47 -08:00
David Harris	68d49c37db	Changed PMA settings in imperas.ic so that peripherals require aligned accesses. This fixes WALLY-trap in ImperasDV.	2023-12-13 20:49:26 -08:00
David Harris	166c98b6f6	Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn	2023-12-13 19:43:17 -08:00
Rose Thompson	9f4c32d49c	Merge branch 'main' of github.com:ross144/cvw	2023-12-13 20:32:59 -06:00
Rose Thompson	e089b421bb	Got it working for the cache.	2023-12-13 20:24:46 -06:00
Rose Thompson	f592baa741	Closer.	2023-12-13 18:15:32 -06:00
Rose Thompson	eeced05f33	More progress towards store delay reduction.	2023-12-13 15:56:29 -06:00
Rose Thompson	f3d43a7713	Progress on reducing store stall in d cache.	2023-12-13 15:34:21 -06:00
David Harris	6c017141c5	Renamed HADE to ADUE for Svadu	2023-12-13 11:49:04 -08:00
Rose Thompson	b2d640d245	Merge branch 'main' of github.com:ross144/cvw	2023-12-04 00:00:56 -06:00
Rose Thompson	8933aef357	Reduced imperas linux run time to 10 seconds.	2023-12-04 00:00:26 -06:00
Rose Thompson	d918791a60	Fixed bug in the wally do script.	2023-11-27 01:26:49 -06:00
Rose Thompson	35a7b2bd24	Last little hickups out of the branch predictor results parsing.	2023-11-27 00:35:22 -06:00
Rose Thompson	3dfca61c3f	Changes to support concurrent simulation of all the branch predictor sweeps.	2023-11-26 22:19:34 -06:00
Rose Thompson	d8f098013c	Merge pull request #506 from davidharrishmc/dev ... Cleanup	2023-11-24 08:45:15 -08:00
David Harris	bcc20c6bd5	Merge pull request #505 from stineje/main ... Update fix for cvtint testbench-fp	2023-11-23 20:43:00 -08:00
David Harris	3df4c13daa	Updated wallyTracer for Linux boot and wally-batch.do to remove buildroot checkpoint support	2023-11-23 20:36:45 -08:00
James E. Stine	1ab7522064	Update fix for cvtint testbench-fp	2023-11-23 17:56:51 -06:00
David Harris	d509644fa6	merged pr	2023-11-21 21:54:33 -08:00
David Harris	d1bb5c7512	Imperas fix for satp modes supported	2023-11-21 21:52:11 -08:00
Rose Thompson	8233ca999f	Changed buildroot to run for 1M instructions only.	2023-11-21 23:46:45 -06:00
Rose Thompson	2767c8b410	Updated imperas.ic to support just sv48 and sv39.	2023-11-21 23:24:16 -06:00
David Harris	6bec559ba6	Removed stale signals from wave.do	2023-11-21 19:49:14 -08:00
Rose Thompson	e5b7301ffe	Updated imperad dv vendor id and architecture id config.	2023-11-21 15:14:17 -06:00
Rose Thompson	b137759b45	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-11-20 10:34:36 -06:00
Rose Thompson	3594c08d4b	Modified linux imperas tests to ... 1. enable zicclsm 2. enable logging at 7000 ms	2023-11-20 10:30:35 -06:00
David Harris	70c58a8ce1	Merge pull request #484 from ross144/main ... Changed bpred-sim.py to only simulate 12 jobs at once.	2023-11-17 13:26:24 -08:00
Rose Thompson	8cf2c404bf	bpred-sim only simulates 12 jobs at once.	2023-11-17 15:21:58 -06:00
David Harris	94201e993f	Merge pull request #481 from ross144/main ... Fixed the BTB logger so sim_bp correctly reports BTB performance	2023-11-15 17:45:38 -08:00
Rose Thompson	9a90c15f37	Extended SeparateBranch to support both just branches and all control flow instructions.	2023-11-15 16:36:49 -06:00
David Harris	cfaeeae25a	Added cmoz support to imperas.ic and adjusted imperas testbench to no longer need FPGA parameter	2023-11-15 08:15:01 -08:00
Rose Thompson	feb45b9b59	Patched up linux imperas testbench.	2023-11-14 14:20:13 -06:00
Rose Thompson	fdb75203cb	Added cbop to to rv32gc.	2023-11-14 10:55:22 -06:00
Rose Thompson	95fc5f4a1c	Towards removing the FPGA config file.	2023-11-13 17:20:26 -06:00
David Harris	426aabbc1a	Imperas commenting	2023-11-10 08:26:32 -08:00
David Harris	7e00581187	Add Svadu support and SPI to imperas configuration	2023-11-10 06:27:25 -08:00
David Harris	625652b9ca	Reporting stall path in synthesis script, support Zcb in Imperas	2023-11-09 06:59:29 -08:00
David Harris	2b183020d5	Fixed bit manpulation on imperas config	2023-11-06 14:11:01 -08:00
David Harris	9c4a7866b8	Fixed Svnapot_page_mask for imperas.ic	2023-11-05 06:51:01 -08:00
David Harris	568aa3c4a6	Verilator improvements	2023-11-04 03:21:07 -07:00
naichewa	fefb5adb8f	code review harris	2023-10-31 12:27:41 -07:00
naichewa	7dd3f24d6c	Merge branch 'main' into spi	2023-10-30 17:01:41 -07:00
naichewa	2330f4ee63	hardware interlock	2023-10-30 17:00:20 -07:00
Rose Thompson	bd04ffc0c9	Fixed bug in bpred-sim.py for btb and class size sweep.	2023-10-24 10:29:02 -05:00
Rose Thompson	ea403e02ff	Updated bpred-sim.py to take command line options to select between sweeping direction, target, class, or ras prediction.	2023-10-23 16:09:40 -05:00
David Harris	b76c371e45	Config file cleanup	2023-10-18 05:38:36 -07:00
David Harris	fab9fbd7f1	Merged testbench	2023-10-16 13:52:24 -07:00