cvw/sim
2023-12-13 21:30:47 -08:00
..
bp-results Last little hickups out of the branch predictor results parsing. 2023-11-27 00:35:22 -06:00
slack-notifier
wave-dos Renamed regression to sim 2023-02-02 14:48:23 -08:00
bpred-sim.py Changes to support concurrent simulation of all the branch predictor sweeps. 2023-11-26 22:19:34 -06:00
buildrootBugFinder.py
coverage tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker 2023-09-02 12:56:36 -07:00
coverage-exclusions-rv64gc.do
FPbuild.txt Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file 2023-06-20 17:26:54 -05:00
fpga-wave.do
GetLineNum.do
imperas.ic Changed PMA settings in imperas.ic so that peripherals require aligned accesses. This fixes WALLY-trap in ImperasDV. 2023-12-13 20:49:26 -08:00
lint-wally Added cbop to to rv32gc. 2023-11-14 10:55:22 -06:00
linux-wave.do
make-tests.sh Renamed regression to sim 2023-02-02 14:48:23 -08:00
Makefile Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn 2023-12-13 19:43:17 -08:00
makefile-memfile
regression-wally Changed buildroot to run for 1M instructions only. 2023-11-21 23:46:45 -06:00
run-imperas-linux.sh Modified linux imperas tests to 2023-11-20 10:30:35 -06:00
run-imperasdv-tests.bash Revert "Update for new layout of ImperasDV files" 2023-06-13 04:17:56 -07:00
rv64gc_CacheSim.py Incorporated new AMO tests from riscv-arch-test 2023-10-16 10:25:45 -07:00
sim-buildroot
sim-buildroot-batch
sim-imperas Revert "Update for new layout of ImperasDV files" 2023-06-13 04:17:56 -07:00
sim-testfloat
sim-testfloat-batch For some reason this was modified - I probably made a mistake - put back vsim 2023-06-22 15:26:22 -05:00
sim-wally hardware interlock 2023-10-30 17:00:20 -07:00
sim-wally-batch code review harris 2023-10-31 12:27:41 -07:00
test
testfloat.do Update fix for cvtint testbench-fp 2023-11-23 17:56:51 -06:00
verilate Verilator improvements 2023-11-04 03:21:07 -07:00
wally-batch.do Fixed bug in the wally do script. 2023-11-27 01:26:49 -06:00
wally-imperas-cov.do add changes for latest IDV file layout 2023-06-16 16:43:53 +01:00
wally-imperas-no-idv.do add changes for latest IDV file layout 2023-06-16 16:43:53 +01:00
wally-imperas.do Added missing files. 2023-10-13 15:10:58 -05:00
wally-linux-imperas.do Reduced imperas linux run time to 10 seconds. 2023-12-04 00:00:26 -06:00
wally.do Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this. 2023-06-14 09:44:52 -07:00
wally.xrun Got xcelium running wally, but it fails to actually preload the memories. 2023-07-12 13:56:57 -05:00
wave-all.do
wave-fpu.do Add reset to wave window 2023-06-29 08:47:16 -05:00
wave.do Changed PMA settings in imperas.ic so that peripherals require aligned accesses. This fixes WALLY-trap in ImperasDV. 2023-12-13 20:49:26 -08:00