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Author	SHA1	Message	Date
Ross Thompson	8698799077	Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.	2022-07-19 22:42:25 -05:00
Katherine Parry	b26297e874	moved ctrl signal registers into fctrl, also a lot of code cleaning	2022-07-20 02:27:39 +00:00
cturek	cce57fdcc5	divsqrt working for floating point	2022-07-20 02:04:20 +00:00
cturek	4e64acf843	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-20 02:00:50 +00:00
cturek	c3a4a2abdf	New radix-2 algorithm implemented and working	2022-07-20 02:00:43 +00:00
David Harris	2b3a5ebefb	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-20 01:49:36 +00:00
David Harris	36bd17984b	Reordered embench Makefile to run size tests first	2022-07-20 01:49:33 +00:00
cturek	0f94177765	small changes	2022-07-20 01:36:25 +00:00
Katherine Parry	70d2b2fdd7	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-19 23:44:41 +00:00
Katherine Parry	d61f84e751	oprimized zeros and replaced complex ?: with always_comb	2022-07-19 23:44:37 +00:00
Daniel Torres	20800b2714	embench no longer launches run automatiacally, need to use make run	2022-07-19 15:16:12 -07:00
Daniel Torres	5b1adc7a67	commented out embench 2.0 tests	2022-07-19 13:36:18 -07:00
Daniel Torres	0668659ac9	made changes to makefile, now builds fastest version (RV64im) by default. Also removed redundent CFLAG funroll-all-loops (was duplicated)	2022-07-19 13:17:02 -07:00
slmnemo	37bf837d48	fixed GPIO test by adding a new function to clear PLIC interrupts	2022-07-19 08:59:16 -07:00
Ross Thompson	a79e5e11f6	Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.	2022-07-18 23:37:18 -05:00
David Harris	8e2069b115	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-19 02:58:13 +00:00
David Harris	b13b49658b	Removed duplicate -march from CoreMark makefile	2022-07-19 02:58:07 +00:00
Katherine Parry	514674417e	moved Se into execute stage	2022-07-19 01:10:10 +00:00
Katherine Parry	64b3e4117b	reworked fmashiftcalc to match book	2022-07-19 00:04:24 +00:00
David Harris	630110e73e	Coremark cleanup	2022-07-18 16:48:13 -07:00
David Harris	9fd772ce83	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-18 23:11:12 +00:00
David Harris	1e87673321	Cleaned up Coremark makefile	2022-07-18 23:10:22 +00:00
Katherine Parry	c89f7f31cc	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-18 20:49:01 +00:00
Katherine Parry	cce5fb8dfd	moved Ss to execute stage	2022-07-18 20:48:56 +00:00
Daniel Torres	aeb6f4266f	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-18 13:30:50 -07:00
Daniel Torres	5a38a15225	added additional changes to coremark to support rv32	2022-07-18 13:30:35 -07:00
Daniel Torres	4883bbb952	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-18 12:13:48 -07:00
Daniel Torres	6a77ada908	added the sail change to spike to let it all run normally	2022-07-18 12:13:15 -07:00
Katherine Parry	7268b4b334	removed underflow from inexactct calculation	2022-07-18 17:51:18 +00:00
Katherine Parry	d6f1fc12db	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-18 17:31:29 +00:00
Katherine Parry	0210718f19	renamed signals in ocde to match book	2022-07-18 17:31:17 +00:00
David Harris	9445ff1440	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-18 10:19:20 +00:00
Ross Thompson	0ef6137ab9	Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.	2022-07-17 21:05:31 -05:00
Ross Thompson	8356e5d742	Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.	2022-07-17 16:20:04 -05:00
James Stine	500191cf34	Add back extractSummary mkdir plots	2022-07-17 13:00:44 -05:00
David Harris	03f573351a	Rewrote convert shift calculation with always for ease of reading	2022-07-17 16:40:58 +00:00
James Stine	bb3c455325	Add import os in extractSummary.py	2022-07-17 11:06:30 -05:00
David Harris	2cbe179a17	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-17 01:40:03 +00:00
David Harris	9514abf0e0	Don't delete hdl directory at end of run	2022-07-17 01:39:57 +00:00
David Harris	622773343f	restored intPending logic to be sticky for PLIC	2022-07-16 17:43:31 -07:00
Katherine Parry	e3ed40620c	forgot some files	2022-07-15 21:42:45 +00:00
Katherine Parry	304c81eb17	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-15 20:17:08 +00:00
Katherine Parry	5cb9c9f319	merged floating-point radix-2 divider with radix-4	2022-07-15 20:16:59 +00:00
cturek	8c57eca262	Square root radix 2 working, does not work with division	2022-07-14 22:52:09 +00:00
cturek	2f96989aab	Square root	2022-07-14 21:19:45 +00:00
cturek	cabd41a5a0	Six tests passing and a bunch of sizizing issues fixed	2022-07-14 19:38:27 +00:00
Katherine Parry	83cc429700	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-14 18:16:13 +00:00
Katherine Parry	2fe8b6e34c	fixed error in divsqrt	2022-07-14 18:16:00 +00:00
cturek	8f7ffc3f29	S and SM are updating but are not correct yet	2022-07-14 00:39:30 +00:00
Katherine Parry	ac2ad1d60a	fixed uncommented line in makefile	2022-07-14 00:01:07 +00:00