bbracker
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c5d393fbc6
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UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses
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2021-11-25 11:01:59 -08:00 |
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Noah Limpert
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cb77c1db3a
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updated fpu instantion on wallypiplinedhart to remove .*, updated spacing as well
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2021-11-24 23:22:04 -08:00 |
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Noah Limpert
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e66fdd3f80
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replaced .* instation of priv module on wallypiplinedhart
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2021-11-24 22:58:59 -08:00 |
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Noah Limpert
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0cd31bfc1f
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Made abhlite instation on wallypipehart more clear, updated spacing for consistency
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2021-11-24 22:48:01 -08:00 |
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Noah Limpert
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8a64510ee4
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updated module instation of LSU on wallypiplinedhard
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2021-11-24 22:09:39 -08:00 |
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bbracker
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de8e2008d2
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fix parseState.py to correctly take in PMPCFG
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2021-11-24 16:52:51 -08:00 |
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Ross Thompson
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b909375289
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Missed another change to uart.
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2021-11-23 10:20:47 -06:00 |
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Ross Thompson
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fe00729d7c
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Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation.
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2021-11-23 10:00:32 -06:00 |
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Ross Thompson
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e309017ec4
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Added QEMU hack for initial LCR value in uart.
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2021-11-22 15:23:19 -06:00 |
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Ross Thompson
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e568068c78
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Hack added to uart so QEMU simulation can work with an ultra fast baud rate relative to the clock speed.
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2021-11-22 15:20:54 -06:00 |
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Ross Thompson
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fcd14828d4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-11-22 11:30:14 -06:00 |
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bbracker
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d90d708cf9
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activate STVAL for buildroot
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2021-11-21 10:40:28 -08:00 |
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Ross Thompson
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c661bb4894
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-11-20 22:44:45 -06:00 |
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Ross Thompson
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d080041508
|
Removed unneeded check for icache ways.
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2021-11-20 22:44:37 -06:00 |
|
Ross Thompson
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baa98e7015
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Reversed bit order in uart.
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2021-11-20 22:43:05 -06:00 |
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Ross Thompson
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4443fca5c5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-11-20 22:37:15 -06:00 |
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Ross Thompson
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2f85ac7f38
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Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
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2021-11-20 22:35:47 -06:00 |
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bbracker
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9e4033935f
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add checkpoints to regression
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2021-11-20 19:42:53 -08:00 |
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bbracker
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13b65fa785
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increase niceness of automatic checkpoint generation
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2021-11-20 12:48:23 -08:00 |
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bbracker
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685534fc20
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-19 20:25:06 -08:00 |
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bbracker
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42ba205c4f
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automatic bug finder script
|
2021-11-19 20:25:00 -08:00 |
|
bbracker
|
5a2a2ca4f5
|
increase buildroot progress expecttions; increase timeout to 20 hours
|
2021-11-19 12:52:11 -08:00 |
|
David Harris
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cde1bbfed4
|
Coremark Diretory cleanup, removed syscall warning about noreturn, rresults are good.
|
2021-11-19 07:39:15 -08:00 |
|
David Harris
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fb3f267645
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Coremark Cleanup, trying compile from addins
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2021-11-19 06:09:04 -08:00 |
|
David Harris
|
c06a7e2bbd
|
Replaced build-coremark.sh with Makefile
|
2021-11-18 20:46:59 -08:00 |
|
David Harris
|
7bdd9b2860
|
exe2memfile don't print when only 1 file
|
2021-11-18 20:37:53 -08:00 |
|
David Harris
|
c45f276f86
|
Moved exe2memfile.pl
|
2021-11-18 20:32:13 -08:00 |
|
David Harris
|
069ea52ac0
|
CoreMark cleanup
|
2021-11-18 20:23:55 -08:00 |
|
David Harris
|
d243f4bcd1
|
Cleaning up CoreMark benchmark
|
2021-11-18 20:12:52 -08:00 |
|
David Harris
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54fef3e2ca
|
vert "Simplifying riscv-coremark"
This reverts commit bdc212cf88.
|
2021-11-18 18:40:13 -08:00 |
|
David Harris
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bdc212cf88
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Simplifying riscv-coremark
|
2021-11-18 17:15:40 -08:00 |
|
David Harris
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f2cf09dd76
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-11-18 16:14:42 -08:00 |
|
David Harris
|
b996598b37
|
CoreMark testing
|
2021-11-18 16:14:25 -08:00 |
|
slmnemo
|
870549c01a
|
Removed .* from hazard hzu(.*).
|
2021-11-17 14:21:23 -08:00 |
|
slmnemo
|
a98dcd11ee
|
Removed .* from hazard hzu(.*) in wallypipelinedhart.sv.
|
2021-11-17 14:08:08 -08:00 |
|
slmnemo
|
fed613dc72
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-11-17 13:38:51 -08:00 |
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slmnemo
|
f4380faa4e
|
removed .* from muldiv.sv (REAL)
|
2021-11-17 13:37:50 -08:00 |
|
David Harris
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b49c419d0b
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-11-17 13:28:33 -08:00 |
|
Noah Limpert
|
0ccc7d5fe8
|
ieu variable naming changed for clarity
|
2021-11-17 13:24:28 -08:00 |
|
slmnemo
|
9fb26d5a61
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-11-17 13:23:20 -08:00 |
|
slmnemo
|
573f8b0c42
|
Removed .*s from muldiv.sv
|
2021-11-17 13:23:12 -08:00 |
|
Noah Limpert
|
ed2285b8e7
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-11-17 13:04:33 -08:00 |
|
Noah Limpert
|
832b23b8a4
|
Updated IFU variable naming for clarity
|
2021-11-17 12:39:05 -08:00 |
|
Kevin Kim
|
d4e9376854
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-11-17 12:18:25 -08:00 |
|
Kevin Kim
|
34b3cc1c8d
|
root level makefile added
|
2021-11-17 12:17:56 -08:00 |
|
Kip Macsai-Goren
|
3f76549a7d
|
renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
|
2021-11-17 10:53:17 -08:00 |
|
Ross Thompson
|
3b8bdc7b2d
|
Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim.
|
2021-11-17 12:47:19 -06:00 |
|
slmnemo
|
39983ab2c6
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-11-17 10:39:52 -08:00 |
|
slmnemo
|
3b4c14e048
|
Removed .* from muldiv.
|
2021-11-17 10:39:18 -08:00 |
|
Ross Thompson
|
11a21899d5
|
Fixed uart by reversing the bit order on transmit.
Set prescale to 0.
|
2021-11-17 10:32:41 -06:00 |
|