Ross Thompson
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f061a26411
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Cleaned up fpga synthesis script.
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2021-12-13 18:26:54 -06:00 |
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Ross Thompson
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b9c8b808ea
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-13 17:16:20 -06:00 |
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Ross Thompson
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7d00649b61
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Formating changes to cache fsms.
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2021-12-13 17:16:13 -06:00 |
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Ross Thompson
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5361f69639
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Fixed some typos in the dcache ptw interaction documentation.
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2021-12-13 15:47:20 -06:00 |
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David Harris
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74cf0eb96a
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-13 07:57:49 -08:00 |
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David Harris
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1ca949c0bb
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Simplified ALU and source multiplexers pass tests
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2021-12-13 07:57:38 -08:00 |
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kwan
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5ede8126fd
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priviledge .* removed, passed regression
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2021-12-13 00:34:43 -08:00 |
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kwan
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b05bc3c19e
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test
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2021-12-13 00:31:51 -08:00 |
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kwan
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83dae9d774
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priviledge .* fixed, passed local regression
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2021-12-13 00:22:01 -08:00 |
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Kevin
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3aad1137c2
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-12 17:53:41 -08:00 |
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Kevin
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b928d01bb8
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dot stars conversions on the rest of the testbenches
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2021-12-12 17:53:26 -08:00 |
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Ross Thompson
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8e39034dbd
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-12 17:33:29 -06:00 |
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Ross Thompson
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2f282e5570
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Revert "Privilige .*s removed"
This reverts commit 471f267987.
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2021-12-12 17:31:57 -06:00 |
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Ross Thompson
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fdbb7b6ef3
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Revert "Priviledged .* removed"
This reverts commit 96ac298596.
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2021-12-12 17:31:39 -06:00 |
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Ross Thompson
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547093b705
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-12 17:21:51 -06:00 |
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Ross Thompson
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bb79f70a63
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Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.
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2021-12-12 17:21:44 -06:00 |
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Ross Thompson
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e6f2a316c8
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Missed constraints file for xilinx ILA.
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2021-12-12 15:06:29 -06:00 |
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Ross Thompson
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b88ec949cf
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Added proper credit to Richard Davis, the author of the original sd card reader.
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2021-12-12 15:05:50 -06:00 |
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kwan
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96ac298596
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Priviledged .* removed
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2021-12-12 09:55:45 -08:00 |
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kwan
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471f267987
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Privilige .*s removed
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2021-12-12 09:54:14 -08:00 |
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David Harris
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d3c3ab3e85
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-12 05:49:31 -08:00 |
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Kevin
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78fbe542a9
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edited one testbench, yet to run regression
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2021-12-10 20:26:20 -08:00 |
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Ross Thompson
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c688b27a20
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Performance counters now output of coremark.
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2021-12-09 14:48:17 -06:00 |
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Ross Thompson
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cd59809e42
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Fixed numerous errors in the preformance counter updates.
Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
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2021-12-09 11:44:12 -06:00 |
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bbracker
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4bc4930ff3
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fix recursive signal logging for graphical sims
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2021-12-08 16:07:26 -08:00 |
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bbracker
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64652be7c5
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-08 14:12:18 -08:00 |
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bbracker
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c97e96f553
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-08 14:12:09 -08:00 |
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bbracker
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6a6835ddc3
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fix release of ReadDataM
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2021-12-08 14:11:43 -08:00 |
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slmnemo
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3ff994f50d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
help
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2021-12-08 14:09:58 -08:00 |
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slmnemo
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094f45e28b
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Removed .* from /wally-pipelined/src/uncore/uart.sv
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2021-12-08 14:02:53 -08:00 |
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Ross Thompson
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a55018b67a
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-08 15:50:43 -06:00 |
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Ross Thompson
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3bdda9687a
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Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict.
Remove preload from dtim.
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2021-12-08 15:50:15 -06:00 |
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David Harris
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9e2c3bef3c
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-08 13:48:49 -08:00 |
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David Harris
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0b63c1cede
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Refactored IEU/ALU logic
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2021-12-08 13:48:04 -08:00 |
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Noah Limpert
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e97dd080a0
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updated fcmp.sv instantiation to remove x*'s
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2021-12-08 13:34:33 -08:00 |
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David Harris
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a174c8b4d7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-08 12:33:59 -08:00 |
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David Harris
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5d4014d351
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Refactoring ALU and datapath muxes
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2021-12-08 12:33:53 -08:00 |
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Ross Thompson
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37451b8978
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-08 13:40:44 -06:00 |
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Ross Thompson
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e1249f4312
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Updated coremark testbench with the extra ports from FPGA merge.
Fixed coremark Makefile to create work directory.
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2021-12-08 13:40:32 -06:00 |
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bbracker
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4060e77b56
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increase regression's expectations of buildroot to 246 million
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2021-12-08 07:01:22 -08:00 |
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slmnemo
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d58f318d39
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Removed .*s from wally-pipelined/src/uncore/uncore.sv
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2021-12-08 01:03:02 -08:00 |
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slmnemo
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52b4802600
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-08 00:26:13 -08:00 |
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Noah Limpert
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feb21d1c4a
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removed .* instantiation from ieu.sv and datapth.sv in ieu folder
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2021-12-08 00:24:27 -08:00 |
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slmnemo
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acacd13ffc
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Removed .* from mmu instance inside lsu.sv.
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2021-12-08 00:15:30 -08:00 |
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Katherine Parry
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d0e708f239
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FMA uses one LOA
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2021-12-07 14:15:43 -08:00 |
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bbracker
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d459e35645
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undo intentionally breaking commit
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2021-12-07 13:43:47 -08:00 |
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bbracker
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3379b74bb2
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intentionally breaking commit
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2021-12-07 13:27:34 -08:00 |
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bbracker
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cf61187273
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undo intentionally breaking commit
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2021-12-07 13:27:06 -08:00 |
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bbracker
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69f025a642
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intentionally breaking commit
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2021-12-07 13:23:19 -08:00 |
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bbracker
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ec6c3bd74c
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2nd attempt at making regression-wally.py able to be run from a different dir
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2021-12-07 13:13:30 -08:00 |
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