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1152 Commits

Author SHA1 Message Date
Ross Thompson
6b42b93886 Now updates the dtim with the dirty data in the dcache. 
Simulation is showing issues.  It lookslike the cache is not
evicting the correct data.
 2021-07-12 15:13:27 -05:00
Ross Thompson
8ca8b9075d Progress towards the test bench flush. 2021-07-12 14:22:13 -05:00
Katherine Parry
a4bd128978 fcvt.sv cleanup 2021-07-11 21:30:01 -04:00
Katherine Parry
0cc07fda1b Almost all convert instructions pass Imperas tests 2021-07-11 18:06:33 -04:00
bbracker
05f9fa65bf rootfs.cpio no longer overlaps 2021-07-11 05:11:12 -04:00
Ross Thompson
282bde7205 Fixed the spurious AHB requests to address 0. Somehow by not having a default 
(else) in the fsm branch selection for STATE_READY in the d cache it was
possible to take an invalid branch through the fsm.
 2021-07-10 22:34:47 -05:00
Ross Thompson
d9fa3af94d Loads are working. 
There is a bug when the icache stalls 1 cycle before the d cache.
 2021-07-10 22:15:44 -05:00
Ross Thompson
a82c4c99c2 Actually writes the correct data now on stores. 2021-07-10 17:48:47 -05:00
Ross Thompson
ee72178eec Write miss with eviction works. 2021-07-10 15:17:40 -05:00
Ross Thompson
0a6c86af94 Write Hits and Write Misses without eviction are working correctly! The next 
step is to add eviction of dirty lines.
 2021-07-10 10:56:25 -05:00
bbracker
e77a9169b6 greatly stripped down unused stuff in linux config 2021-07-10 11:53:35 -04:00
David Harris
488cfa16ff Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 19:18:35 -04:00
David Harris
e6fb590187 added missing tlbmixer.sv 2021-07-09 19:18:23 -04:00
bbracker
4556098f0a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 18:56:28 -04:00
bbracker
e4f62e32ba fix_mem.py bugfix 2021-07-09 18:56:17 -04:00
Ross Thompson
94b29ec418 Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address. 
I think this is do to the cycle latency of stores.  We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a
full cache block or a word write from the CPU.
 2021-07-09 17:14:54 -05:00
bbracker
b2cb86d55c organize/update buildroot scripts for new image 2021-07-09 17:03:47 -04:00
Ross Thompson
7e98610651 Design loads in modelsim, but trap is an X. 2021-07-09 15:37:16 -05:00
Ross Thompson
6abd23a61d Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented. 
Also faults and the dcache ptw interlock are not implemented.
 2021-07-09 15:16:38 -05:00
David Harris
ef2bcf6ea7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 07:53:30 -04:00
David Harris
b09fd0d0a8 Simplified tlbmixer mux to and-or 2021-07-08 23:34:24 -04:00
David Harris
4d53a935b3 Fixed missing stall in InstrRet counter 2021-07-08 20:08:04 -04:00
bbracker
5736fdecbb organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files 2021-07-08 19:18:11 -04:00
Ross Thompson
2efb7a4f81 Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache. 2021-07-08 18:03:52 -05:00
Ross Thompson
6041aef263 completed read miss branch through dcache fsm. 
The challenge now is to connect to ahb and lsu.
 2021-07-08 17:53:08 -05:00
David Harris
230654ea76 Eliminate reserved bits from TLB RAM 2021-07-08 17:35:00 -04:00
David Harris
f806707cb0 Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram 2021-07-08 16:58:11 -04:00
David Harris
b1592a0542 TLB cleanup to match diagrams 2021-07-08 16:52:06 -04:00
Ross Thompson
4c5aee3042 This d cache fsm is getting complex. 2021-07-08 15:26:16 -05:00
Ross Thompson
adcc7afffa Partial implementation of the data cache. Missing the fsm. 2021-07-07 17:52:16 -05:00
David Harris
dc44ca4b0b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-07 06:32:29 -04:00
David Harris
6dc49dd073 Renamed tlb ReadLines to Matches 2021-07-07 06:32:26 -04:00
Abe
09a092abd5 Updated MISA defining as well as porting sizes for peripherals (34 to 56) 2021-07-07 02:37:09 -04:00
Abe
244e197348 Changed SvMode to SVMode on line 76 2021-07-06 23:28:58 -04:00
David Harris
1301f4df7f Added ASID matching for CAM 2021-07-06 18:56:25 -04:00
Kip Macsai-Goren
1652e09b38 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 18:54:41 -04:00
David Harris
2b26bbbbd7 more TLB name touchups 2021-07-06 18:39:30 -04:00
Kip Macsai-Goren
8dfa28125f fixed upper bits page fault signal 2021-07-06 18:32:47 -04:00
David Harris
73024fee2d connected signals in tlb by name instead of .* 2021-07-06 17:22:10 -04:00
David Harris
18f4fa600a changed tlbphysicalpagemask to structural 2021-07-06 17:16:58 -04:00
David Harris
404ba5988a changed tlbphysicalpagemask to structural 2021-07-06 17:08:04 -04:00
David Harris
78850bfcd8 MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB 2021-07-06 15:29:42 -04:00
Ross Thompson
dc4c26d2a2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-06 13:45:20 -05:00
Ross Thompson
d85bf23af3 Merged several of the load/store/instruction access faults inside the mmu. 
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
 2021-07-06 13:43:53 -05:00
bbracker
0e708a72f3 more completely uncomment MMU tests to make sim wally work 2021-07-06 14:33:52 -04:00
Abe
79e62b7c53 Disabled MCOUNTINHIBIT to enable csr counters (changed to 32'h0 on line 140) 2021-07-06 12:37:58 -04:00
Ross Thompson
61f870809d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-06 10:41:45 -05:00
Ross Thompson
71a23626d5 Fixed bug in the LSU pagetable walker interlock. 2021-07-06 10:41:36 -05:00
David Harris
6d25ea1508 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 10:44:17 -04:00
David Harris
4c2cbe3200 Cleaned up tlb output muxing 2021-07-06 10:44:05 -04:00
David Harris
087bed3b67 Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines 2021-07-06 10:38:30 -04:00
Kip Macsai-Goren
35f89f9e99 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 10:16:34 -04:00
David Harris
69c0358ffd Created tlbcontrol module to hide details 2021-07-06 03:25:11 -04:00
David Harris
6785ed9994 Implemented TSR, TW, TVM, MXR status bits 2021-07-06 01:32:05 -04:00
David Harris
3cb9e5acd3 Fixed adrdecs to use Access signals for TIMs 2021-07-05 23:42:58 -04:00
David Harris
a390736f26 Don't generate HPTW when MEM_VIRTMEM=0 2021-07-05 23:35:44 -04:00
David Harris
e3f6758265 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-05 23:23:17 -04:00
David Harris
8ca7abaa02 Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0 2021-07-05 20:35:31 -04:00
Ross Thompson
4d9b87a823 Fixed combo loop in the page table walker. 2021-07-05 16:37:26 -05:00
Ross Thompson
59913e13aa Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-05 16:07:27 -05:00
Kip Macsai-Goren
770420b448 added new mmu tests to makefrag and commented out in the testbench 2021-07-05 10:54:30 -04:00
David Harris
e65fb5bb35 Added F_SUPPORTED flag to disable floating point unit when not in MISA 2021-07-05 10:30:46 -04:00
David Harris
b8b7fab02b Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported 2021-07-04 19:33:46 -04:00
David Harris
bbbc1d2f89 Simplified PLIC with generate 2021-07-04 19:17:15 -04:00
David Harris
ce3edd0288 Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb 2021-07-04 19:02:56 -04:00
David Harris
39fa84efdd Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb 2021-07-04 18:56:30 -04:00
David Harris
d2e3e14cbc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-04 18:55:24 -04:00
David Harris
57e1111df3 Gave names to for loops in generate blocks for ease of reference 2021-07-04 18:52:16 -04:00
bbracker
825900565c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-04 18:17:16 -04:00
David Harris
cc04009f82 Touched up TLB D and A bit checks 2021-07-04 18:17:09 -04:00
bbracker
11606e96f1 ICacheCntrl now reacts differently to InstrPageFaultF vs ITLBWriteF 2021-07-04 18:17:06 -04:00
Ross Thompson
058c37b5b1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 17:07:57 -05:00
David Harris
595df47a3e Fixed TLB_ENTRIES merge conflict and handling of global PTEs 2021-07-04 18:05:22 -04:00
Ross Thompson
e198f348da Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:54:31 -05:00
Ross Thompson
2c56e30c73 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:53:16 -05:00
David Harris
71268cc0e8 Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:53:08 -04:00
David Harris
6b9cfe90d8 Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:52:00 -04:00
Ross Thompson
f2c4df0a5b Removed the TranslationVAdrQ as it is not necessary. 2021-07-04 16:49:34 -05:00
bbracker
a20afc6e1a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-04 17:20:55 -04:00
bbracker
96939328ea for GPIO give priority to clearing interrupts 2021-07-04 17:20:16 -04:00
Ross Thompson
8e48865140 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:19:39 -05:00
David Harris
d138d6545d Restructured TLB Read as AND-OR operation with one-hot match/read line 2021-07-04 17:01:22 -04:00
David Harris
b59213c83f Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders 2021-07-04 16:33:13 -04:00
David Harris
deae60eb1d TLB cleanup 2021-07-04 14:59:04 -04:00
Ross Thompson
8ae0a5bd7d relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic. 2021-07-04 13:49:38 -05:00
David Harris
243c03f870 TLB cleanup 2021-07-04 14:37:53 -04:00
David Harris
fed096407b TLB minor organization 2021-07-04 14:30:56 -04:00
David Harris
a5c0dc8c81 Fixed MPRV and MXR checks in TLB 2021-07-04 13:20:29 -04:00
David Harris
5b891e05ac TLB mux and swizzling cleanup 2021-07-04 12:53:52 -04:00
David Harris
622060b99f Replaced generates with arrays in TLB 2021-07-04 12:32:27 -04:00
David Harris
b5df9b282d Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries 2021-07-04 11:39:59 -04:00
David Harris
9276446797 Switched to array notation for pmpchecker 2021-07-04 10:51:56 -04:00
David Harris
c016ab8e58 Commented out some unused modules 2021-07-04 01:40:27 -04:00
David Harris
1bd353c1d7 Merge conflict on linux-waves.do 2021-07-04 01:22:10 -04:00
David Harris
c897bef8cd Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
bbracker
17ef10568f optionally output GDB-formatted instruction list to main buildroot folder 2021-07-03 17:25:19 -04:00
Ross Thompson
9b959715a0 removed mmustall and finished port annotations on ptw and lsuArb. 2021-07-03 16:06:09 -05:00
Ross Thompson
fd088f8ecd Added explicit names to lsu, lsuarb and pagetable walker to make the code refactoring process eaiser. 2021-07-03 15:51:25 -05:00
Ben Bracker
66692af57c src/cache/ICacheCntrl.sv 2021-07-03 11:24:41 -05:00
Ben Bracker
d6c7dc02ed fix ICache indenting 2021-07-03 11:11:07 -05:00