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Author SHA1 Message Date
Ross Thompson
e531b0103e Fixed wally64/32priv test hangup. 
The fix for the issue 203 had a lingering bug which did not suppress a bus access if the hptw short circuits on a pma/p fault.
 2023-04-05 23:13:45 -05:00
Kevin Thomas
159c02e3f3 Merge branch 'main' of https://github.com/kjprime/cvw 2023-04-05 17:44:54 -05:00
Kevin Thomas
7c1ecfd97d Merge branch 'openhwgroup:main' into main 2023-04-05 17:44:47 -05:00
Kevin Thomas
d7188d6d9c Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 17:43:43 -05:00
Ross Thompson
7cdd12a40a Merge pull request #206 from AlecVercruysse/coverage2 
i$ coverage improvements
 2023-04-05 17:29:35 -05:00
David Harris
02053c5dc6 Merge pull request #210 from SydRiley/main 
Starting to extend fpu conditional coverage, reformatting ifu test cases.
 2023-04-05 14:56:16 -07:00
Alec Vercruysse
ac3569d75c Update ram1p1rwe (ce & we) coverage exlusion explanation 2023-04-05 14:54:58 -07:00
Sydeny
9e3d78de8b Starting to extend fpu conditional coverage, reformating ifu test cases 2023-04-05 14:10:15 -07:00
Kevin Thomas
dab5074f29 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 15:33:10 -05:00
Kevin Thomas
4d30aff198 Formating white space 2023-04-05 15:30:55 -05:00
David Harris
32c5a1d83e Merge pull request #205 from kbox13/my-single-change 
Increase LSU Coverage
 2023-04-05 13:16:04 -07:00
Kevin Thomas
5ac49fa31f Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 15:04:12 -05:00
David Harris
1257439cf8 Merge pull request #208 from ross144/main 
Fixes Issue 203
 2023-04-05 13:03:30 -07:00
Ross Thompson
70aa5a5917 Merge pull request #207 from AlecVercruysse/cachesim 
Cache Simulator
 2023-04-05 14:59:52 -05:00
Ross Thompson
da9cf02ba0 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 14:55:12 -05:00
Limnanthes Serafini
590f95d353 *.out removal 2023-04-05 12:50:26 -07:00
Limnanthes Serafini
baa537c5d3 *.out removal 2023-04-05 12:50:10 -07:00
Limnanthes Serafini
ecc580a140 *.out removal 2023-04-05 12:49:57 -07:00
Alec Vercruysse
570e86afc3 Make CacheWay flush and dirty logic dependent on !READ_ONLY_CACHE 
To increase coverage. Read-only caches do not have flushes since
they do not have dirty bits.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
54df581ce6 make Cache Flush Logic dependent on !READ_ONLY_CACHE 
read-only caches do not have flush logic since they do not have to
deal with dirty bits.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
3419ef3651 remove ClearValid from cache 
The cachefsm hardwired ClearValid logic to zero.
This signal might've been added to potentially add extra functionality
later. Unless that functionality is added, however, it negatively
impacts coverage. If the goal is to maximize coverage, this signal
should be removed and only added when it becomes necessary.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
81125d3180 change i$ cachetagmem from ram1p1rwbe -> ram1p1rwe 
the byte write-enables were always tied high, so we can use
RAM without byte-enable to increase coverage.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
782feb6161 turn off ce coverage for ram1p1rwe 
According to the textbook, the cache memory chip enable,
`CacheEn`, is only lowered by the cachefsm with it is in the ready
state and a pipeline stall is asserted.

For read only caches, cache writes only occur in the state_write_line
state. So there is no way that a write would happen while the chip
enable is low.

Removing the chip-enable check from this memory to increase coverage
would be a bad idea since if anyone else uses this ram, the behaviour
would be differently than expected. Instead, I opted to turn off
coverage for this statement. Since this ram, which does not have a
byte enable, is used exclusively by read-only caches right now, this
should not mistakenly exclude coverage for other cases, such as D$.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
8b6b96012d add ram1p1rwe for read-only cache ways (remove byte-enable) 
- increases coverage
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
2553321158 fix typo in cachway setValid input comment 2023-04-05 11:48:18 -07:00
Alec Vercruysse
9df246e5de put cacheLRU coverage explanation on another line 
the `: explanation` syntax was not working
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
af113c7268 Exclude CacheLRU log2 function from coverage 2023-04-05 11:48:18 -07:00
Ross Thompson
394f2d65f2 Progress on bug 203. 2023-04-05 13:20:04 -05:00
Kevin Box
0f13148215 Add sfence.vma 2023-04-05 10:34:30 -07:00
Kevin Box
333bb87b05 Revert "Add sfence.vma and arch64d/f tests to increase coverage in the LSU" 
This reverts commit 28a9faa265.
 2023-04-05 10:32:25 -07:00
Kevin Box
89abad65fa remove testing changes 2023-04-05 10:27:34 -07:00
Kevin Box
a516cbdf88 remove testing change 2023-04-05 10:27:11 -07:00
Kevin Box
28a9faa265 Add sfence.vma and arch64d/f tests to increase coverage in the LSU 2023-04-05 10:18:41 -07:00
Limnanthes Serafini
9cbc2a8e4c Merge remote-tracking branch 'upstream/main' into cachesim 2023-04-05 09:53:05 -07:00
Kevin Thomas
0c80067d45 Minor change with the IFU in the decompress module, in the compressed instruction truth table. 
The truth table is already fully covered, removed redundant last case checking
 2023-04-05 10:27:52 -05:00
David Harris
7c71c21810 Merge pull request #201 from ross144/main 
Improved d/i cache loggers
 2023-04-05 06:40:14 -07:00
Limnanthes Serafini
6ad5d81980 Further comments and attribution. 2023-04-05 02:46:31 -07:00
Limnanthes Serafini
49226a1eb2 Commenting, attribution for sim, minor log changes 2023-04-05 02:43:02 -07:00
Limnanthes Serafini
0aadbd8492 Outfiles for the failing tests. 2023-04-05 02:42:09 -07:00
Limnanthes Serafini
53cff56a97 Changed logging enables, debug mode in sim. 2023-04-04 23:49:35 -07:00
Limnanthes Serafini
6f7620e7c1 CacheSim edits, tests. I/D$ logging, Lim's version 2023-04-04 21:12:35 -07:00
Noah Limpert
6bcd47db99 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-04 20:22:00 -07:00
Limnanthes Serafini
d4653a6a42 Merge branch 'openhwgroup:main' into cachesim 2023-04-04 13:15:56 -07:00
Ross Thompson
02909b3c57 Fixed the d cache logger. 2023-04-04 14:19:19 -05:00
Ross Thompson
87e88a798f Improved d/i cache logger. 2023-04-04 13:38:32 -05:00
Ross Thompson
dd1cbbc6e1 Merge pull request #199 from davidharrishmc/dev 
Fixed WFI to commit when an interrupt occurs
 2023-04-04 11:34:24 -05:00
David Harris
4552f9cf8c Fixed WFI to commit when an interrupt occurs 2023-04-04 09:32:26 -07:00
David Harris
b4288bf53f Merge pull request #198 from eroom1966/main 
add support for Sstc
 2023-04-04 09:23:38 -07:00
eroom1966
adafc8037d add support for Sstc 2023-04-04 17:20:00 +01:00
Ross Thompson
52d1c19509 Merge pull request #194 from davidharrishmc/dev 
Bit manipulation support in ImperasDV.  Test improvements.
 2023-04-04 09:13:27 -05:00