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1061 Commits

Author SHA1 Message Date
Katherine Parry
bc8d660bc5 FPU forwarding reworked pt.1 2021-06-24 18:39:18 -04:00
bbracker
ced5039776 Revert "fixed forwarding" 
This reverts commit 0f4a4a6ade.
 2021-06-24 17:39:37 -04:00
Ross Thompson
d8183e59e4 Works until pma checker breaks the simulation by reading HADDR rather than data physical address. 2021-06-24 14:42:59 -05:00
Ross Thompson
732551d6be Fixed combo loop in between the page table walker and i/dtlb. 2021-06-24 13:47:10 -05:00
Ross Thompson
0377d3b2c9 Progress. 2021-06-24 13:05:22 -05:00
bbracker
0f4a4a6ade fixed forwarding 2021-06-24 11:20:21 -04:00
bbracker
3ae4cd951a make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses 2021-06-24 08:35:00 -04:00
bbracker
3d6b422e34 regression can overcome the fact that buildroots UART prints stuff 2021-06-24 02:00:01 -04:00
bbracker
409a73604c whoops meant to remove notifications from busybear, not buildroot 2021-06-24 01:54:46 -04:00
bbracker
55cf205222 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-24 01:42:41 -04:00
bbracker
b84419ff4e overhauled linux testbench and spoofed MTTIME interrupt 2021-06-24 01:42:35 -04:00
Kip Macsai-Goren
547bf1d0af added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day. 2021-06-23 19:59:06 -04:00
Ross Thompson
abe5bc90bf Partial addition of page table walker arbiter. 2021-06-23 17:03:54 -05:00
Ross Thompson
6134c22aca Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two. 
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
 2021-06-23 16:43:22 -05:00
Katherine Parry
44af47608c fpu clean-up 2021-06-23 16:42:40 -04:00
Ross Thompson
d5063bee7d Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache. 2021-06-23 15:13:56 -05:00
Ross Thompson
5de7a46237 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-23 09:34:42 -05:00
David Harris
718630c378 Reduced complexity of pmpadrdec 2021-06-23 03:03:52 -04:00
David Harris
4189b2d4a7 Reduced complexity of pmpadrdec 2021-06-23 02:31:50 -04:00
David Harris
1972d83002 Refactored pmachecker to have adrdecs used in uncore 2021-06-23 01:41:00 -04:00
David Harris
6dc54acde8 renamed dmem to lsu and removed adrdec module from pmpadrdec 2021-06-22 23:03:43 -04:00
bbracker
ae0fa90450 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-22 18:28:30 -04:00
bbracker
b43a8885cd give EBU a dedicated PMA unit as just an address decoder 2021-06-22 18:28:08 -04:00
Ross Thompson
e7d8d0b337 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-22 15:47:16 -05:00
Katherine Parry
9eb6eb40bf rv64f FLW passes imperas tests 2021-06-22 16:36:16 -04:00
Kip Macsai-Goren
d6c5c61b59 Fixed mask assignment error, made usage, variables more clear 2021-06-22 13:31:06 -04:00
Kip Macsai-Goren
b78c09baed Continued fixing fsm to work right with svmode 2021-06-22 13:29:49 -04:00
Kip Macsai-Goren
852bb9296f updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop 2021-06-22 11:21:11 -04:00
bbracker
56b0d4d016 added slack notifier for long sims 2021-06-22 08:31:41 -04:00
Ross Thompson
03084a4128 Icache now uses physical lenght bits rather than XLEN. 2021-06-21 16:41:09 -05:00
Ross Thompson
8ec5b0c4f1 Improved some names in icache. 2021-06-21 16:40:37 -05:00
David Harris
82515862e3 Commented out 100k tests to improve speed 2021-06-21 01:43:18 -04:00
David Harris
29ad38fb9e Added Physical Address and Size to PMA Checker/MMU 2021-06-21 01:27:02 -04:00
David Harris
aef408af58 Reversed [0:...] with [...:0] in bus widths across the project 2021-06-21 01:17:08 -04:00
David Harris
0a59b006ab Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals 2021-06-20 22:59:04 -04:00
bbracker
83a1f29c37 remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR 2021-06-20 22:38:25 -04:00
bbracker
5afad80432 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-20 22:29:40 -04:00
bbracker
665a67f442 linux actually uses FPU now! 2021-06-20 22:29:21 -04:00
Katherine Parry
26bad083ad all rv64f instructions except convert, divide, square root, and FLD pass 2021-06-20 20:24:09 -04:00
bbracker
1f2a967e0f read from MSTATUS workaround because QEMU has incorrect MSTATUS 2021-06-20 10:11:39 -04:00
bbracker
2611d214a6 testbench update b/c QEMU extends 32b CSRs to 64b 2021-06-20 09:24:19 -04:00
bbracker
7aa2f0d953 make xCOUNTEREN what buildroot expects it to be 2021-06-20 09:22:31 -04:00
bbracker
6e9c6e3e6a whoops wavedo typo 2021-06-20 05:36:54 -04:00
bbracker
9469367da3 make buildroot ignore SSTATUS because QEMU did not originally log it 2021-06-20 05:31:24 -04:00
bbracker
78f4703dc9 MSTATUS workaround 2021-06-20 04:48:09 -04:00
bbracker
927d99cf3b workaround for ignoring MTIME 2021-06-20 02:26:39 -04:00
bbracker
52fb630379 remove lingering busybear stuff from buildroot do files 2021-06-20 00:50:53 -04:00
bbracker
124ef980e3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-20 00:40:44 -04:00
bbracker
3e32ba3684 make buildroot waves only turn on after a user-specified point 2021-06-20 00:39:30 -04:00
Ross Thompson
bb756849a7 Revert "Icache now uses physical lenght bits rather than XLEN." 
This reverts commit d4de8a54a2.
 2021-06-19 08:58:34 -05:00
Ross Thompson
e4c932265d Revert "Improved some names in icache." 
This reverts commit 22ea801edb.
 2021-06-19 08:58:32 -05:00
bbracker
ebe893b70c change buildroot config to use relative path for testvectors 2021-06-18 22:28:07 -04:00
bracker
3d99c9c2c4 gitignore merge 2021-06-18 21:12:05 -05:00
bracker
ed75172f21 handle tera usernames more gracefully 2021-06-18 21:11:14 -05:00
bbracker
10ca2ac5bc on-Tera solution for sym linking to linux testvectors 2021-06-18 22:01:18 -04:00
bracker
a9f9ef1180 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 20:41:01 -05:00
bracker
8a8b0dcfd7 script support for copying large files from tera 2021-06-18 20:40:19 -05:00
bbracker
f394b91515 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 17:37:49 -04:00
bbracker
f84a689c19 fixed PCtext error by using blocking assignments 2021-06-18 17:37:40 -04:00
Ross Thompson
0250d52ae3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-18 12:24:42 -05:00
Ross Thompson
22ea801edb Improved some names in icache. 2021-06-18 12:22:41 -05:00
Ross Thompson
d4de8a54a2 Icache now uses physical lenght bits rather than XLEN. 2021-06-18 12:02:59 -05:00
David Harris
43bc17350b Restored wally-busybear testbench now that graphical sim is working 2021-06-18 12:36:25 -04:00
bbracker
958f60c704 restore graphical buildroot sim 2021-06-18 11:58:16 -04:00
Abe
892c14430b Updated directory coremark_bare's wally-config file to define PMP_ENTRIES 2021-06-18 11:46:25 -04:00
bbracker
1e93bbd119 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 09:49:37 -04:00
bbracker
72f1e3eab6 buildroot added to regression because it passes regression 2021-06-18 09:49:30 -04:00
David Harris
21a55458ca Made MemPAdrM and related signals PA_BITS wide 2021-06-18 09:36:22 -04:00
David Harris
a3f3533cce Changed physical addresses to PA_BITS in size in MMU and TLB 2021-06-18 09:11:31 -04:00
bbracker
0980ce92bc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 08:15:40 -04:00
bbracker
8ae333a6b2 remove unused testbench-busybear.sv 2021-06-18 08:15:19 -04:00
David Harris
cc78504ae4 Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX 2021-06-18 08:13:15 -04:00
David Harris
72d8d34e3c allow all size memory access in CLINT; added underscore to peripheral address symbols 2021-06-18 08:05:50 -04:00
David Harris
e03912f64c Cleaned up name of MTIME register in CSRC 2021-06-18 07:53:49 -04:00
David Harris
8357b14957 Further cleaning of PMA checker 2021-06-17 22:27:39 -04:00
David Harris
91a13999a9 Added SUPPORTED to each peripheral in each config file 2021-06-17 21:36:32 -04:00
David Harris
5e7ed4bd88 added inputs to pmaadrdec 2021-06-17 18:54:39 -04:00
David Harris
09c5e27853 Started simplifying PMA checker 2021-06-17 16:28:06 -04:00
bbracker
076469230f added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version 2021-06-17 12:09:10 -04:00
bbracker
db0abfd36d enable TIME CSR for 32 bit mode as well 2021-06-17 11:34:16 -04:00
bbracker
7d1469a06c provide time and timeh CSRs based on CLINT's counter 2021-06-17 08:38:30 -04:00
bbracker
832e4fc7e3 making linux waveforms more useful 2021-06-17 08:37:37 -04:00
bbracker
0647094e73 PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable 2021-06-17 05:19:36 -04:00
bbracker
e93e528aa1 changed parsedCSRs2] to parsedCSRs 2021-06-17 05:18:14 -04:00
bbracker
902fd85e9c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-17 00:50:14 -04:00
bbracker
7de660f8aa still not sure if QEMU workaround is correct, but here is all linux progress so far 2021-06-17 00:50:02 -04:00
bbracker
7a652139b5 mcause test fixes and s-mode interrupt bugfix 2021-06-16 17:37:08 -04:00
bbracker
3f6b018f66 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-16 16:17:53 -04:00
bracker
d1bab12e1e chmod +x'd privileged testgen scripts 2021-06-16 10:28:57 -05:00
bbracker
8d8d2aabc2 fixed incorrect expectation fof CLINT spec 2021-06-15 19:24:24 -04:00
bbracker
6f1f585c2c Merge remote-tracking branch 'origin/fixPrivTests' into main 2021-06-15 09:57:46 -04:00
Katherine Parry
920ff984ca Updated FMA 2021-06-14 13:42:53 -04:00
David Harris
5e01f71c52 disabled Verilator WIDTH warnings in ICCacheCntrl 2021-06-12 19:50:06 -04:00
Ross Thompson
5d7ca87982 fixed the mtime register. 2021-06-11 13:50:13 -05:00
James E. Stine
171a6728b0 Put repository of fpdivsqrt with RTL-based adder instead of structural implementation 2021-06-11 14:35:22 -04:00
bracker
11a84f64b8 attempt no 1: just change out x28s for x31s 2021-06-11 12:39:28 -05:00
David Harris
79ee817d91 Reverted MIDELEG and MEDELEG to XLEN so busybear passes 2021-06-10 23:47:32 -04:00
David Harris
690e2b7f31 Restored counter events 2021-06-10 11:18:58 -04:00
David Harris
0e4e091a39 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-10 10:47:55 -04:00
David Harris
c3d106f0f0 Removed two cycles of latency from the DTIM 2021-06-10 10:30:24 -04:00
bbracker
9c3cb0d2bf peripheral lint fixes 2021-06-10 10:19:10 -04:00
bbracker
f0266f621b merge 2021-06-10 10:03:01 -04:00
bbracker
31e1c926f2 attempt to fix regression by adding PMP_ENTRIES to configs 2021-06-10 09:59:26 -04:00
bbracker
3e7126e0c2 buildroot progress -- able to mimic GDB output 2021-06-10 09:58:20 -04:00
bbracker
58d0e46d02 UART improved and added more reg read side effects 2021-06-10 09:53:48 -04:00
David Harris
17b76d4cd7 Configurable number of performance counters 2021-06-10 09:41:26 -04:00
David Harris
6dcf86948c Restored PCCorrectE declaration in IFU 2021-06-09 21:09:16 -04:00
David Harris
e231fc6b00 More verilator fixes, but bpred is broken 2021-06-09 21:03:03 -04:00
David Harris
3fb378dcf0 removed verilator lint_off WIDTH 2021-06-09 21:01:44 -04:00
David Harris
9dd3857c26 Fixed lint WIDTH errors 2021-06-09 20:58:20 -04:00
David Harris
4bd7058456 More PMP entries 2021-06-08 15:33:06 -04:00
David Harris
9a17556de4 Start to parameterize number of PMP Entries 2021-06-08 15:29:22 -04:00
Kip Macsai-Goren
fcb9b1f0e1 working version with new mmu comments, old boottim values 2021-06-08 15:20:25 -04:00
Kip Macsai-Goren
b37eebfe4d merge of reverted main into up to date main 2021-06-08 14:57:43 -04:00
Kip Macsai-Goren
3b5627b753 reverted to working version with new mmu comments 2021-06-08 14:56:00 -04:00
David Harris
cfe5c27946 Resized BOOT TIM to 1 KB 2021-06-08 14:04:32 -04:00
Kip Macsai-Goren
6ed96761b6 Merge small mmu changes into main 2021-06-08 14:00:26 -04:00
Kip Macsai-Goren
be99c18002 making mmu branch line up with main 2021-06-08 13:59:03 -04:00
Kip Macsai-Goren
41ceb20296 some cleanup of signals, not done yet 2021-06-08 13:39:32 -04:00
bbracker
17960a6484 Ah big ole merge! Passes sim-wally-batch and linting, so should be fine 2021-06-08 12:41:25 -04:00
bbracker
5026a42fac * GPIO comprehensive testing 
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
 2021-06-08 12:32:46 -04:00
Kip Macsai-Goren
e044f72e59 remove redundant decodes, fixed mmu logic ins/outs 2021-06-07 19:23:30 -04:00
Kip Macsai-Goren
146ed95bdb got rid of some underscores in filenames, modules 2021-06-07 18:54:05 -04:00
Kip Macsai-Goren
46b2b19792 implemented simpler page mixers, cleaned up a bit 2021-06-07 18:32:34 -04:00
Kip Macsai-Goren
55d50f5607 began updating cam line to reduce muxes, confusion 2021-06-07 17:03:31 -04:00
Kip Macsai-Goren
1377680270 regression working partially done page mask 2021-06-07 17:02:31 -04:00
David Harris
4740ef97d6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-07 16:14:13 -04:00
David Harris
c3d21967f8 Simplified superpage matching 2021-06-07 16:11:28 -04:00
Katherine Parry
b55798f09b lint is clean 2021-06-07 14:22:54 -04:00
bbracker
3e11da2aa2 temporarily removing buildroot from regression until it is regenerated 2021-06-07 13:20:50 -04:00
David Harris
b37bcc8e38 Continued merge 2021-06-07 12:49:47 -04:00
David Harris
1e67db2f0c Second attept to commit refactoring config files 2021-06-07 12:37:46 -04:00
David Harris
95cc70295b Merge difficulties 2021-06-07 09:50:23 -04:00
David Harris
8bbabb683d Refactored configuration files and renamed testbench-busybear to testbench-linux 2021-06-07 09:46:52 -04:00
Katherine Parry
e4db6ea6f5 fixed lint warnings for fpu and lzd 2021-06-05 12:06:33 -04:00
Kip Macsai-Goren
d69501c4fa Cleaned up some unused signals 2021-06-04 21:04:19 -04:00
Kip Macsai-Goren
b99b5f8e0e moved privilege dfinitions into wally-constants, upgraded relevant includes 2021-06-04 17:55:07 -04:00
Kip Macsai-Goren
4a00fbaf04 Merge branch 'mmu' into main 
new mmu unit and moving pmp/pma now passes regression except for lint and buildroot
 2021-06-04 17:07:56 -04:00
Kip Macsai-Goren
318a547531 added shared constants file list of includes 2021-06-04 17:05:47 -04:00
Kip Macsai-Goren
7e41b17e65 restructured so that pma/pmp are a part of mmu 2021-06-04 17:05:07 -04:00
Ross Thompson
6f58c66be8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-04 15:16:39 -05:00
Ross Thompson
e200b4b5a4 Continued I-Cache cleanup. 
Removed strange mux on InstrRawD along with
the select logic.
 2021-06-04 15:14:05 -05:00
Ross Thompson
35afdecda2 Moved I-Cache offset selection mux to icache.sv (top level). 
When we switch to set associative this is will be more efficient.
 2021-06-04 13:49:33 -05:00
Ross Thompson
fdc7c673dd Cleaned up the I-Cache memory. 2021-06-04 13:36:06 -05:00
Katherine Parry
19116ed889 Double-precision FMA instructions 2021-06-04 14:00:11 -04:00
Ross Thompson
2c16591396 Reorganized the icache names. 2021-06-04 12:53:42 -05:00
Ross Thompson
147be536f1 Relocated the icache to the cache directoy. 2021-06-04 12:23:46 -05:00
David Harris
b836679ae1 Started MMU 2021-06-04 11:59:14 -04:00
David Harris
99d661cee9 Fixed RV32 MMU constants 2021-06-04 09:15:42 -04:00
David Harris
a61411995a moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00