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Author SHA1 Message Date
bbracker
e93e528aa1 changed parsedCSRs2] to parsedCSRs 2021-06-17 05:18:14 -04:00
bbracker
902fd85e9c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-17 00:50:14 -04:00
bbracker
7de660f8aa still not sure if QEMU workaround is correct, but here is all linux progress so far 2021-06-17 00:50:02 -04:00
bbracker
7a652139b5 mcause test fixes and s-mode interrupt bugfix 2021-06-16 17:37:08 -04:00
bbracker
3f6b018f66 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-16 16:17:53 -04:00
bracker
d1bab12e1e chmod +x'd privileged testgen scripts 2021-06-16 10:28:57 -05:00
bbracker
8d8d2aabc2 fixed incorrect expectation fof CLINT spec 2021-06-15 19:24:24 -04:00
David Harris
b69992872e Added page tables to MMU tests 2021-06-15 17:54:13 -04:00
Kip Macsai-Goren
e9977b1702 added page table example file, continued work on mmu test 2021-06-15 16:13:37 -04:00
David Harris
1d8c5683a3 Started WALLY-MMU 2021-06-15 11:52:16 -04:00
bbracker
2f53adf557 whoops forgot RV32 2021-06-15 11:33:01 -04:00
bbracker
cda9a1d8e6 apply changes to privileged tests 2021-06-15 11:32:10 -04:00
bbracker
6f1f585c2c Merge remote-tracking branch 'origin/fixPrivTests' into main 2021-06-15 09:57:46 -04:00
Katherine Parry
920ff984ca Updated FMA 2021-06-14 13:42:53 -04:00
David Harris
5e01f71c52 disabled Verilator WIDTH warnings in ICCacheCntrl 2021-06-12 19:50:06 -04:00
Ross Thompson
5d7ca87982 fixed the mtime register. 2021-06-11 13:50:13 -05:00
James E. Stine
171a6728b0 Put repository of fpdivsqrt with RTL-based adder instead of structural implementation 2021-06-11 14:35:22 -04:00
bracker
11a84f64b8 attempt no 1: just change out x28s for x31s 2021-06-11 12:39:28 -05:00
David Harris
79ee817d91 Reverted MIDELEG and MEDELEG to XLEN so busybear passes 2021-06-10 23:47:32 -04:00
David Harris
690e2b7f31 Restored counter events 2021-06-10 11:18:58 -04:00
David Harris
0e4e091a39 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-10 10:47:55 -04:00
David Harris
c3d106f0f0 Removed two cycles of latency from the DTIM 2021-06-10 10:30:24 -04:00
bbracker
9c3cb0d2bf peripheral lint fixes 2021-06-10 10:19:10 -04:00
bbracker
f0266f621b merge 2021-06-10 10:03:01 -04:00
bbracker
31e1c926f2 attempt to fix regression by adding PMP_ENTRIES to configs 2021-06-10 09:59:26 -04:00
bbracker
3e7126e0c2 buildroot progress -- able to mimic GDB output 2021-06-10 09:58:20 -04:00
bbracker
58d0e46d02 UART improved and added more reg read side effects 2021-06-10 09:53:48 -04:00
David Harris
17b76d4cd7 Configurable number of performance counters 2021-06-10 09:41:26 -04:00
David Harris
6dcf86948c Restored PCCorrectE declaration in IFU 2021-06-09 21:09:16 -04:00
David Harris
077777b019 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-09 21:03:16 -04:00
David Harris
e231fc6b00 More verilator fixes, but bpred is broken 2021-06-09 21:03:03 -04:00
David Harris
3fb378dcf0 removed verilator lint_off WIDTH 2021-06-09 21:01:44 -04:00
David Harris
9dd3857c26 Fixed lint WIDTH errors 2021-06-09 20:58:20 -04:00
bbracker
3fb5f1df24 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-09 15:14:49 -04:00
bbracker
7ed83b3ebc log only half of bootmem for memory map convenience -- works ok for now because bootmem is half empty 2021-06-09 15:14:42 -04:00
David Harris
4bd7058456 More PMP entries 2021-06-08 15:33:06 -04:00
David Harris
9a17556de4 Start to parameterize number of PMP Entries 2021-06-08 15:29:22 -04:00
Kip Macsai-Goren
fcb9b1f0e1 working version with new mmu comments, old boottim values 2021-06-08 15:20:25 -04:00
Kip Macsai-Goren
b37eebfe4d merge of reverted main into up to date main 2021-06-08 14:57:43 -04:00
Kip Macsai-Goren
3b5627b753 reverted to working version with new mmu comments 2021-06-08 14:56:00 -04:00
David Harris
cfe5c27946 Resized BOOT TIM to 1 KB 2021-06-08 14:04:32 -04:00
Kip Macsai-Goren
6ed96761b6 Merge small mmu changes into main 2021-06-08 14:00:26 -04:00
Kip Macsai-Goren
be99c18002 making mmu branch line up with main 2021-06-08 13:59:03 -04:00
Kip Macsai-Goren
41ceb20296 some cleanup of signals, not done yet 2021-06-08 13:39:32 -04:00
bbracker
17960a6484 Ah big ole merge! Passes sim-wally-batch and linting, so should be fine 2021-06-08 12:41:25 -04:00
bbracker
5026a42fac * GPIO comprehensive testing 
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
 2021-06-08 12:32:46 -04:00
Kip Macsai-Goren
e044f72e59 remove redundant decodes, fixed mmu logic ins/outs 2021-06-07 19:23:30 -04:00
Kip Macsai-Goren
146ed95bdb got rid of some underscores in filenames, modules 2021-06-07 18:54:05 -04:00
Kip Macsai-Goren
46b2b19792 implemented simpler page mixers, cleaned up a bit 2021-06-07 18:32:34 -04:00
Kip Macsai-Goren
55d50f5607 began updating cam line to reduce muxes, confusion 2021-06-07 17:03:31 -04:00