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1,744 Commits 5 Branches 2 Tags 53 MiB
e93014d6d8
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71 Commits

Author SHA1 Message Date
David Harris
e93014d6d8 Moved divide iteration register names to M stage 2021-10-10 11:30:53 -07:00
David Harris
e8d013b106 Simplified remainder for divide by 0 2021-10-10 11:20:07 -07:00
David Harris
94fd682cdc divider control signal simplificaiton 2021-10-10 10:55:02 -07:00
David Harris
bfe8bf3855 Removed negedge flops from divider 2021-10-10 10:41:13 -07:00
David Harris
99fd79c20b Simplified divider sign handling 2021-10-10 08:35:26 -07:00
David Harris
eaa8be14b9 renamed DivStart 2021-10-10 08:32:04 -07:00
David Harris
5cb30164d4 renamed DivSigned 2021-10-10 08:30:19 -07:00
bbracker
25e0745a6a fix div restarting bug 2021-10-07 18:55:00 -04:00
David Harris
cc41d40d61 Divider cleaup 2021-10-03 11:22:34 -04:00
David Harris
3398328bf1 Divider cleanup 2021-10-03 11:16:48 -04:00
David Harris
9809e57d0c Replacing XE and DE with SrcAE and SrcBE in divider 2021-10-03 11:11:53 -04:00
David Harris
bf0061be66 Reduced cycle count for DIVW/DIVUW by two 2021-10-03 09:42:22 -04:00
David Harris
bd61ec544b Divider comments cleanup 2021-10-03 01:12:40 -04:00
David Harris
30ec68d567 Parameterized number of bits per cycle for integer division 2021-10-03 01:10:15 -04:00
David Harris
078ddfd341 Divider cleanup 2021-10-03 00:41:41 -04:00
David Harris
8f36297569 Added suffixes to more divider signals 2021-10-03 00:32:58 -04:00
David Harris
dcbbee6623 More divider cleanup 2021-10-03 00:20:35 -04:00
David Harris
6aa2521959 Eliminated extra inversion for subtraction in divider 2021-10-03 00:10:12 -04:00
David Harris
371f9d9a4a Added more pipeline stage suffixes to divider 2021-10-03 00:06:57 -04:00
David Harris
24bb3f4baf Added more pipeline stage suffixes to divider 2021-10-02 22:54:01 -04:00
David Harris
3441991d93 Divider mostly cleaned up 2021-10-02 21:10:35 -04:00
David Harris
67690c2ed7 Partial divider cleanup 3 2021-10-02 21:00:13 -04:00
David Harris
775520c05a Partial divider cleanup 2 2021-10-02 20:57:54 -04:00
David Harris
fe69513bb7 Partial divider cleanup 2021-10-02 20:55:37 -04:00
David Harris
a86ce5cd37 Divider code cleanup 2021-10-02 10:41:09 -04:00
David Harris
d532bde931 Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division 2021-10-02 10:36:51 -04:00
David Harris
d4437b842a Divider code cleanup 2021-10-02 10:13:49 -04:00
David Harris
0e0e204d3d Moved negating divider otuput to M stage 2021-10-02 10:03:02 -04:00
David Harris
735132191c Moved muldiv result selection to M stage for performance 2021-10-02 09:38:02 -04:00
David Harris
73d852b1ef Divide performs 2 steps per cycle 2021-10-02 09:19:25 -04:00
David Harris
a8573a27d4 Integer Divide/Rem passing all regression. 2021-09-30 20:07:22 -04:00
David Harris
953c8931ed RV32 div/rem working signed and unsigned 2021-09-30 15:24:43 -04:00
David Harris
e1ad732178 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00
David Harris
b2fe8eddc0 Restored old integer divider 2021-09-12 22:07:52 -04:00
David Harris
1f6e4c71fc Modified rxfull determination in UART, started division 2021-09-12 20:00:24 -04:00
Ross Thompson
4c8ea89f15 Fixed syntax errors in some floating point modules. This came up in 
Xilinx synthesis.
 2021-08-15 16:48:49 -05:00
David Harris
b8b7fab02b Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported 2021-07-04 19:33:46 -04:00
David Harris
57e1111df3 Gave names to for loops in generate blocks for ease of reference 2021-07-04 18:52:16 -04:00
David Harris
c016ab8e58 Commented out some unused modules 2021-07-04 01:40:27 -04:00
David Harris
9dd3857c26 Fixed lint WIDTH errors 2021-06-09 20:58:20 -04:00
Katherine Parry
b55798f09b lint is clean 2021-06-07 14:22:54 -04:00
James E. Stine
7f5e5287b0 delete div.bak 2021-06-01 17:39:54 -04:00
James E. Stine
bccdd2c137 Updates to muldiv.sv for 32-bit div/rem 2021-06-01 15:31:07 -04:00
James E. Stine
927aec34a2 Modify muldiv.sv to handle W instructions for 64-bits 2021-05-31 23:27:42 -04:00
James E. Stine
a71b97e878 Cosmetic changes on integer divider 2021-05-31 09:16:30 -04:00
James E. Stine
2f365a9e07 Add enhancements to integer divider including: 
- better comments
  - optimize FSM to end earlier
  - passes for 32-bit or 64-bit depending on parameter to intdiv

Left div.bak in just in case have to revert back to original for now.
 2021-05-31 09:12:21 -04:00
James E. Stine
889b935630 Modify elements of generics for LZD and shifter wrote for integer 
divider.
 2021-05-31 08:36:19 -04:00
James E. Stine
bbc1dfb309 Minor cosmetic elements on div.sv 2021-05-24 19:30:28 -05:00
James E. Stine
1704fdc877 Mod for DIV/REM instruction and update to div.sv unit 2021-05-24 19:29:13 -05:00
James E. Stine
49cc330bd9 Forgot initialization config for div - apologies 2021-05-17 17:12:27 -05:00