10 Commits

Author	SHA1	Message	Date
Rose Thompson	dfe5ef4427	Added logic for the non-cache atomics.	2024-01-15 17:47:17 -06:00
Rose Thompson	82a786f185	Hmm. Verilator is complaining about the parameter width. I'm not sure why so I changed to 1 bit.	2024-01-15 17:36:01 -06:00
Rose Thompson	614a83331f	Fixed part of issue #405. ... The non-cache version of the bus controller did not have the correct supression of BusCommitted for a read only controller.	2024-01-15 17:29:00 -06:00
Rose Thompson	588e1caeba	Found bugs in the no I$ implementation's abhinterface width. We were only testing XLEN=32. XLEN=64 did not properly align instructions not aligned to 8 byte boundaries.	2024-01-06 22:29:16 -06:00
Harshini Srinath	dbdb3c69d3	Update ahbinterface.sv ... Program clean up	2023-06-10 18:18:16 -07:00
Ross Thompson	1299319d0b	More parameterization. Based on Lim's work. EBU, IFU (except bpred), and IEU done.	2023-05-24 14:56:02 -05:00
Ross Thompson	052bc95966	More parameterization. Copied Lim. Still no slow down.	2023-05-24 14:49:22 -05:00
Limnanthes Serafini	53847269da	More changes	2023-04-13 21:02:15 -07:00
Ross Thompson	b518177a45	Updated EBU to replace tabs with spaces.	2023-03-24 15:01:38 -05:00
David Harris	78eb90715c	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00