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90 Commits

Author SHA1 Message Date
rachanaerra
10ff69efc1 updated constraints file 2022-12-05 15:05:21 -06:00
Ross Thompson
e99a424ddc Updated top level fpga file. 2022-11-18 11:10:45 -06:00
Ross Thompson
70d7fca750 Updated fpga wave configuration. 2022-11-16 15:57:19 -06:00
Ross Thompson
cf00f85456 Updated vcu118 constraints to run cpu at 38.43Mhz. 2022-11-15 10:19:38 -06:00
Ross Thompson
cc80f1f7b2 Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s). 
Increased CPU clock speed from 30 Mhz to 35 Mhz.
 2022-11-11 15:33:03 -06:00
Ross Thompson
30b2bd263c Updates to fpga constraints. 2022-11-09 13:52:36 -06:00
Ross Thompson
5c49cc4dd0 Fixed bug with fpga makefile. 2022-11-07 09:20:05 -06:00
Jacob Pease
160ca366c8 Added PLIC signals for debugging on FPGA. 2022-10-25 13:57:09 -05:00
Ross Thompson
9ba487c323 Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 15:38:39 -05:00
Ross Thompson
92ace4d8f7 Forget to include updated xdc file. 2022-10-24 13:51:21 -05:00
Ross Thompson
a008c61939 Updated debug2.xdc for interlock fsm changes. 2022-10-19 17:34:47 -05:00
Ross Thompson
92accfb1a6 Updated uart settings and fpga wave config. 2022-10-18 15:05:33 -05:00
Ross Thompson
2d063bbb2d Updated constraints file to work with alternate uart. 2022-10-04 17:35:44 -05:00
Ross Thompson
16e10a4c5b added new constraints for fpga. 2022-09-17 22:20:06 -05:00
Ross Thompson
787f5bcccb Fixed fpga debug constraints. 2022-09-03 17:36:29 -05:00
Ross Thompson
53995c2ed3 update to fpga wave. 2022-09-02 15:54:54 -05:00
Ross Thompson
5d2b299182 Fixed brom1p1r.sv to have fpga preload. 2022-09-02 15:49:50 -05:00
Ross Thompson
4d60d9a840 Fixed up FPGA constraints. 
Added back in the fpga boot rom preload.
 2022-09-02 13:54:35 -05:00
Ross Thompson
01a7718471 Added generate around ebu. 2022-08-25 09:24:13 -05:00
Ross Thompson
701324eeb8 Updated ila signals. 
Improve fpga wave config.
added back in the fpga preload.
 2022-08-25 09:03:29 -05:00
Ross Thompson
8180d1ade4 Updated fpga debugger to latest RTL version. 2022-08-19 17:13:36 -05:00
Ross Thompson
8b2491c169 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-19 16:39:28 -05:00
Ross Thompson
83bca570ae Modified debugger for updated rtl. 2022-06-04 14:39:55 -05:00
Ross Thompson
1318f702cf Added more debug signals to uart. 2022-05-21 19:47:40 -05:00
Ross Thompson
db85afcd2d Added more plic debugging signals. 2022-05-21 14:04:08 -05:00
Ross Thompson
6cae5aa88f Updated the fpga constraints. 2022-05-21 13:32:03 -05:00
Ross Thompson
9079e67aae Updated fpga debugger. 2022-05-17 23:04:01 -05:00
Ross Thompson
51add16def Updated debugger constraints. 2022-05-09 10:19:25 -05:00
Ross Thompson
c045e3afd8 Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
Ross Thompson
82356342f0 Added another GPR to debugger. 2022-04-17 18:12:05 -05:00
Ross Thompson
c16dec88de Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00
Ross Thompson
7d0462dc59 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
43a294dc88 Added signals to ila. 2022-04-07 21:09:50 -05:00
Ross Thompson
9db8471bf2 Added sp to ila. 2022-04-07 16:29:41 -05:00
Ross Thompson
7abde2b566 Increazed fpga clock speed to 35Mhz. 
linux boot is much faster.
 2022-04-05 15:09:49 -05:00
Ross Thompson
64846c800e Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
Ross Thompson
5ef6cde52e Added more ILA signals. 2022-04-02 16:39:45 -05:00
Ross Thompson
0340c0fd44 Added wave config 
added new signals to ILA.
 2022-04-01 12:44:14 -05:00
Ross Thompson
cb945a6a6a Added PLIC to ILA. 2022-03-31 16:44:49 -05:00
Ross Thompson
4f1258043d Updated constraints file. 2022-03-30 17:48:44 -05:00
Ross Thompson
9f9a273d2c Added bootrom.txt. 2022-03-30 17:29:48 -05:00
Ross Thompson
b3506c755a test. 2022-03-28 17:04:58 -05:00
Ross Thompson
f818b2a428 Updated debug2.xdc ila constraints to match rtl. 2022-03-28 10:52:26 -05:00
Ross Thompson
111e02677d Fixed ila's config. 2022-02-11 13:58:45 -06:00
Ross Thompson
6a82ee0579 Fixed debug2.xdc to match wally changes. 2022-02-08 15:23:44 -06:00
Ross Thompson
b621eb78fb Updated debug2 ila signal names. 2022-01-28 11:43:49 -06:00
Ross Thompson
1bb8d36308 Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
Ross Thompson
728e46a794 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-25 19:21:04 -06:00
Ross Thompson
db197b6491 Added pin location for reset on VCU118 board. Somehow this was missing and still worked. 2022-01-25 17:48:42 -06:00
Ross Thompson
71eb1df492 Added comport.setup to remind how to configure com port for xilinx fpga. 
Added load-deadlock.tsm to trigger load operation deadlock.
 2022-01-25 14:54:38 -06:00