Jarred Allen
665c244ba1
Fix another bug in the icache (why so many of them?)
2021-03-20 17:54:40 -04:00
Jarred Allen
43a8cb0354
Revert "Change flop to listen to StallF"
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This reverts commit f069b759be
2021-03-20 17:34:19 -04:00
Jarred Allen
f069b759be
Change flop to listen to StallF
2021-03-20 17:04:13 -04:00
Jarred Allen
50c961bbe4
Merge changes from main
2021-03-18 18:58:10 -04:00
Shreya Sanghai
dfc86539cc
Merge branch 'gshare' into main
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Conflicts:
wally-pipelined/regression/wave.do
2021-03-18 17:25:48 -04:00
Ross Thompson
9386e6a524
Switched to gshare from global history.
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Fixed a few minor bugs.
2021-03-18 16:05:59 -05:00
Ross Thompson
181a28e875
Fixed minor bug with the size of gshare.
2021-03-18 16:00:09 -05:00
Shreya Sanghai
f35d3b39c8
removed unnecesary PC registers in ifu
2021-03-18 16:31:21 -04:00
Thomas Fleming
062c4d40da
Connect tlb, pagetablewalker, and memory
2021-03-18 14:35:46 -04:00
Shreya Sanghai
d9b1e7d67f
added gshare and global history predictor
2021-03-16 17:03:01 -04:00
Jarred Allen
3fc36b978d
Fix icache for jumping into misaligned instructions
2021-03-16 16:57:51 -04:00
Shreya Sanghai
a79e26f9d8
added global history branch predictor
2021-03-16 16:06:40 -04:00
Jarred Allen
5b174adc2a
Fix BEQZ tests
2021-03-14 15:42:27 -04:00
Jarred Allen
003242ae8a
Merge upstream changes
2021-03-14 14:57:53 -04:00
Jarred Allen
c2f2caa3f6
Get non-jump case working
2021-03-14 14:46:21 -04:00
Ross Thompson
ccaaa829ce
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-12 14:58:04 -06:00
Ross Thompson
0637874cac
Cleanup of the branch predictor flush and stall controls.
2021-03-12 14:57:53 -06:00
Thomas Fleming
e57b6cf18c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-03-11 00:15:58 -05:00
Jarred Allen
c0ee17b6ac
Merge upstream changes
2021-03-09 21:20:34 -05:00
Jarred Allen
81b29a3891
More progress
2021-03-09 21:16:07 -05:00
Ross Thompson
9a93193d6a
Oups. I forgot to update other do files with the commands to preload the branch predictor memories.
2021-03-05 15:23:53 -06:00
Thomas Fleming
97e9baa316
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 13:35:44 -05:00
Thomas Fleming
e48dc38869
Export SATP_REGW from csrs to MMU modules
2021-03-05 01:22:53 -05:00
Jarred Allen
5da98b5381
Partial progress towards compressed instructions
2021-03-04 18:30:26 -05:00
Jarred Allen
b0f4d8e8d4
Remove rd2, working for non-compressed
2021-03-04 16:46:43 -05:00
Ross Thompson
619bbd9d83
Merge branch 'bp' into main
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Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
Ross Thompson
a8cd4f2b2e
Fixed forwarding around the 2 bit predictor.
2021-03-04 13:01:41 -06:00
Ross Thompson
d0223da2f7
Converted to using the BTB to predict the instruction class.
2021-03-04 09:23:35 -06:00
Thomas Fleming
8c410b6fbe
Install dtlb in dmem
2021-03-04 03:30:06 -05:00
Thomas Fleming
1a2db17ee5
Install tlb into ifu
2021-03-04 03:11:34 -05:00
Ross Thompson
6191fcb1af
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
David Harris
0258901865
Cleaned out unused signals
2021-02-26 09:17:36 -05:00
David Harris
225102047a
Clean up bus interface code
2021-02-26 01:03:47 -05:00
David Harris
38b8cc652c
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
Ross Thompson
c856003f73
RAS needs to be reset or preloaded. For now I just reset it.
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Fixed bug with the instruction class.
Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.
2021-02-19 20:09:07 -06:00
Ross Thompson
597dd1e7e6
Added FlushF to hazard unit.
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Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
2021-02-19 16:36:51 -06:00
Ross Thompson
7d6093b302
Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.
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About 149307ns of simulation run.
2021-02-18 21:32:15 -06:00
Ross Thompson
bbe0db3ebe
Integrated the branch predictor into the hardward. Not yet working.
2021-02-17 22:19:17 -06:00
Ross Thompson
ca546beaf8
We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.
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This is not yet tested but the system verilog does compile.
2021-02-15 14:51:39 -06:00
David Harris
cc42655789
More memory interface, ALU testgen
2021-02-15 10:10:50 -05:00
Ross Thompson
935e9e59e9
added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior.
2021-02-14 15:13:55 -06:00
Ross Thompson
8486f426b7
The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables.
2021-02-14 11:06:31 -06:00
David Harris
842c374de9
Debugging instruction fetch
2021-02-09 11:02:17 -05:00
David Harris
33110ed636
Data memory bus integration
2021-02-07 23:21:55 -05:00
David Harris
429f48e766
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
92bf1674b4
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
David Harris
07af481b67
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
