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Author SHA1 Message Date
Kip Macsai-Goren
ced763beb6 Added GPIO loopback to let outputs cause interrupts 2022-04-18 07:22:49 +00:00
Kip Macsai-Goren
121cc627f6 Added working trap test to regression, fixed hanfling of some interrupts 2022-04-18 07:22:16 +00:00
Shreya Sanghai
1f229c5387 automate synth 2022-04-18 04:21:03 +00:00
Shreya Sanghai
9538338d8e added frequency configs for makefile 2022-04-18 04:21:03 +00:00
Shreya Sanghai
6f0085201b replaced k with bpred size 2022-04-18 04:21:03 +00:00
Shreya Sanghai
a8b3cc8cf9 added bpred size to wally config 2022-04-18 04:21:03 +00:00
David Harris
22842816a8 LSU name cleanup 2022-04-18 03:18:38 +00:00
Ross Thompson
61dbf13a69 Fixed bug I introduced by csrc cleanup and changes to ILA. 2022-04-17 21:45:46 -05:00
David Harris
e04febdb57 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-18 01:30:11 +00:00
David Harris
c07b9d1722 Renamed FinalAMOWriteDataM to AMOWriteDataM 2022-04-18 01:30:03 +00:00
David Harris
6504017044 Run 4M instructions in buildroot test to get through kernel & VirtMem startup 2022-04-18 01:29:38 +00:00
Ross Thompson
a5d4e39e7d Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
Ross Thompson
0bcfd9d666 Added another GPR to debugger. 2022-04-17 18:12:05 -05:00
Ross Thompson
3add26be64 fixed no forcing bug in linux testbench. 2022-04-17 17:49:51 -05:00
David Harris
d8b4c985cd Remvoed bytemask anding from FinalWriteDataM in subwordwrite 2022-04-17 22:33:25 +00:00
David Harris
6bb4cd1bca Prefix comparator cleanup 2022-04-17 21:53:11 +00:00
David Harris
5bb521635e Experiments with prefix comparator; minor fixes in WFI and testbench warnings 2022-04-17 21:43:12 +00:00
Kip Macsai-Goren
ecacd5d36b removed broken test from makefrag 2022-04-17 21:25:56 +00:00
Kip Macsai-Goren
331efcedc4 added new tests to makefrag and tests.vh 2022-04-17 21:00:36 +00:00
Kip Macsai-Goren
1a9c312700 added more comprehensive vectoring, interrupt causing and handing 2022-04-17 20:57:12 +00:00
Kip Macsai-Goren
1af47c9d25 Added the rest of the tests lited in Chapter 5 test plan 2022-04-17 20:57:12 +00:00
Ross Thompson
5a6ad32688 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-17 15:23:46 -05:00
Ross Thompson
7135364d1a Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00
David Harris
b4902a6ff9 First implementation of WFI timeout wait 2022-04-17 17:20:35 +00:00
David Harris
6769f0cb43 Added comments in fcvt 2022-04-17 16:53:10 +00:00
David Harris
d71940d96d Simplified SLT logic 2022-04-17 16:49:51 +00:00
Ross Thompson
55c667b60d Commented output power analysis to speed simulation. 2022-04-16 15:32:59 -05:00
Ross Thompson
b3153bc71e Updated wally to point to riscv-arch-test tag 2.7.3 2022-04-16 15:32:43 -05:00
Ross Thompson
881695582b commented out wally-scratch test as it hangs during compile. 2022-04-16 15:09:17 -05:00
Ross Thompson
f8bdb6db49 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-16 14:59:03 -05:00
Ross Thompson
bfc68bef69 Fixed possible bugs in LRSC. 2022-04-16 14:45:31 -05:00
James E. Stine
be917cdee6 Update mkdir in run_all.sh to guarantee no errors 2022-04-14 22:23:23 -05:00
David Harris
0932d4df46 Added WFI support to IFU to keep it in the pipeline 2022-04-14 17:26:17 +00:00
David Harris
c3bca40e05 Added WFI to the testbench instruction name decoder 2022-04-14 17:12:11 +00:00
David Harris
6e16922aae WFI should set EPC to PC+4 2022-04-14 17:05:22 +00:00
bbracker
0e183be3e5 fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM 2022-04-14 09:23:21 -07:00
bbracker
489ce4269a fix ReadDataM forcing 2022-04-13 15:32:00 -07:00
bbracker
20c82b6f1a parsePlicState.py bugfix 2022-04-13 13:04:43 -07:00
Ross Thompson
65573f07b7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 13:39:47 -05:00
bbracker
c697c17b05 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 05:35:56 -07:00
bbracker
016e960401 change interrupt spoofing to happen at negative clock edges 2022-04-13 04:31:23 -07:00
bbracker
3465d8cd32 improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS 2022-04-13 03:37:53 -07:00
bbracker
0d4ec9b3f9 fix bugs in PLIC checkpoint state parsing 2022-04-13 01:59:21 -07:00
bbracker
1bb5e1f35b whoops fix address for PLIC int enables in checkpoint generation 2022-04-13 01:36:09 -07:00
bbracker
67ef47b25b whoops forgot to update AttemptedInstructionCount in interrupt spoofing 2022-04-13 00:49:37 -07:00
bbracker
6c3d274970 change testbench-linux to by default use attempted instruction count for warning/error messages 2022-04-12 21:22:08 -07:00
Ross Thompson
2eb2263e94 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 19:38:04 -05:00
Ross Thompson
adb4e30c45 Missed the force on uart for no tracking. 2022-04-12 19:37:44 -05:00
Ross Thompson
d087deef65 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 17:56:48 -05:00
Ross Thompson
22f2e88553 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00