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Missed the force on uart for no tracking.

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This commit is contained in:
Ross Thompson 2022-04-12 19:37:44 -05:00
parent 56bea58a3c
commit adb4e30c45
1 changed files with 5 additions and 3 deletions
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8
pipelined/testbench/testbench-linux.sv
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@ -27,7 +27,7 @@
`include "wally-config.vh"
`define DEBUG_TRACE 2
`define DEBUG_TRACE 0
// Debug Levels
// 0: don't check against QEMU
// 1: print disagreements with QEMU, but only halt on PCW disagreements
@ -544,9 +544,11 @@ module testbench;
// override on special conditions \
if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) \
//$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, InstrCountW-1); \
force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
if(!NO_IE_MTIME_CHECKPOINT) \
force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
else \
release dut.core.ieu.dp.ReadDataM; \
if(!NO_IE_MTIME_CHECKPOINT) \
release dut.core.ieu.dp.ReadDataM; \
if(textM.substr(0,5) == "rdtime") begin \
//$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \
if(!NO_IE_MTIME_CHECKPOINT) \