Jacob Pease
1ca8673c43
Added help option to the flash-sd script.
2023-08-22 13:37:33 -05:00
Ross Thompson
087d418c35
Updateds to vcu118 constraints and device tree.
2023-08-02 16:51:32 -05:00
Ross Thompson
f35b05e608
Added new signals to the vcu118 debug4 ila to help figure out why the new linux build's hptw fails.
2023-08-02 16:14:04 -05:00
Ross Thompson
49ee1ea62a
Clean up vcu118 synth scripts.
2023-08-01 14:39:33 -05:00
Ross Thompson
1b237a14a1
Pushed performance of arty a7 to 23Mhz.
2023-07-31 14:13:09 -05:00
Jacob Pease
87a6ad5a87
Removed non-existent SDC dependency from VCU targets in FPGA Makefile.
2023-07-27 15:01:20 -05:00
Ross Thompson
717833b11a
Removed all old references to the old flash card controller.
...
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
2023-07-24 15:45:57 -05:00
Ross Thompson
fd187e9ee6
Merge branch 'main' of github.com:ross144/cvw
2023-07-24 10:47:05 -05:00
Ross Thompson
d239b0649e
Improved timing constraints for arty a7 to push clock speed to 20Mhz.
2023-07-24 10:46:49 -05:00
Ross Thompson
6e17cfba03
At least it simulates and gets through fpga elaboration.
2023-07-21 18:40:26 -05:00
Ross Thompson
3eeecd2f27
Merge branch 'boot' into mergeBoot
...
Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Jacob Pease
36785848a5
Working new boot process. Buildroot package for sdc.
2023-07-20 14:15:59 -05:00
Ross Thompson
7873d26678
Fixed a bunch of timing constraints for the arty a7 board.
2023-07-19 17:08:16 -05:00
Ross Thompson
3bf2b35704
Wow. The newest version of Vivado does not like the enums as parameters.
...
The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
2023-07-18 15:07:10 -05:00
Ross Thompson
626a918668
FPGA updates.
2023-06-20 11:11:34 -05:00
Ross Thompson
25103176a0
Updated fpga wave config.
2023-06-19 12:28:30 -05:00
Ross Thompson
8242544efa
Updated fpga wally wrapper to work with the ILA.
2023-06-19 12:15:48 -05:00
Ross Thompson
24b8c6c391
I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug.
2023-06-16 17:00:27 -05:00
Ross Thompson
4bee446cad
Vivado requires an intermediate wrapper file for parameterization.
2023-06-16 16:30:14 -05:00
Ross Thompson
2f35bec970
FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization.
2023-06-16 15:40:13 -05:00
Jacob Pease
2ad9c72acc
The Vivado-RISC-V SDC works. Wally is now booting through it.
2023-05-26 15:42:33 -05:00
Ross Thompson
86de36b6ce
FPGA makefile update.
2023-04-25 16:24:26 -05:00
Ross Thompson
d513956bb9
Updated fpga Makefile to work with both the Arty and VCU platforms.
2023-04-21 11:08:35 -05:00
Jacob Pease
53de2bf782
AHB triggers write, but AXI side doesn't update.
2023-04-18 15:23:22 -05:00
Ross Thompson
2df6c6cb0f
It's almost working.
2023-04-18 14:24:59 -05:00
Ross Thompson
ac95087042
Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V.
2023-04-17 20:05:59 -05:00
Ross Thompson
fad0366d26
Adding in the ILA to the arty a7.
2023-04-17 14:54:10 -05:00
Ross Thompson
0be81fdfc8
Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster.
2023-04-17 12:16:31 -05:00
Ross Thompson
a7a362f82e
Finally got the arty a7 to build.
2023-04-17 11:54:22 -05:00
Ross Thompson
9070b4adf5
OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :(
2023-04-17 11:10:19 -05:00
Ross Thompson
5da5b76449
Fixed more issues with arty a7 constarints.
2023-04-16 13:25:02 -05:00
Ross Thompson
d2272c0620
Found and fixed the major architecture issue with the mig 7 used in the arty a7 board.
...
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
2023-04-15 11:13:28 -05:00
Ross Thompson
c9445384d7
Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure.
2023-04-14 18:02:16 -05:00
Ross Thompson
b5799c896e
Finally fixed the ddr3 mig script to work correclty.
2023-04-14 11:41:51 -05:00
Ross Thompson
679dc7d73b
Progress on arty a7 board.
2023-04-13 17:57:12 -05:00
Ross Thompson
b015e736a0
Updated to help debut Jacob's crossbar woes.
2023-04-11 14:22:42 -05:00
Ross Thompson
6123efd5b2
Updates for arty a7.
2023-04-10 17:02:19 -05:00
Ross Thompson
2abd164d03
Fixed syntax errors in arty7 top level.
2023-04-10 16:08:40 -05:00
Ross Thompson
81fb076e9e
Added more support for Arty A7 board.
2023-04-10 16:01:17 -05:00
Ross Thompson
d2d528cf3c
Finally building ddr3 xilinx ip from script.
2023-04-10 14:36:33 -05:00
Ross Thompson
5aa614858f
Started putting together the arty a7 board package files.
2023-04-10 13:15:55 -05:00
Ross Thompson
b57566e632
Added Jacob's ILA script.
2023-04-06 15:32:36 -05:00
Jacob Pease
2822cb273c
AXI Crossbar is working. Fixed address width in generator script.
2023-02-22 15:13:16 -06:00
Jacob Pease
5161fd25cc
Merge branch 'main' of github.com:openhwgroup/cvw into boot
2023-02-16 17:36:26 -06:00
David Harris
99d179dd3e
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
Jacob Pease
536039ad86
Modified makefile. Added axi protocol converter IP.
2023-01-23 19:30:29 -06:00
Jacob Pease
24d0b1c860
Added extra core signal to mark_debug.txt. Modified wally.tcl
2023-01-23 17:00:24 -06:00
Jacob Pease
204fb84708
Merge branch 'main' of github.com:openhwgroup/cvw into boot
2023-01-23 12:41:02 -06:00
Ross Thompson
442de3f5b7
Updated fpga constraints.
2023-01-20 20:16:33 -06:00
Ross Thompson
a4822c9f54
Added license and comments to new script.
2023-01-20 19:50:33 -06:00
