Ross Thompson 2f35bec970 FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization.		2023-06-16 15:40:13 -05:00
..
debug	Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.	2022-10-24 15:38:39 -05:00
bootrom.txt	Added bootrom.txt.	2022-03-30 17:29:48 -05:00
insert_debug_comment.sh	Updated fpga constraints.	2023-01-20 20:16:33 -06:00
Makefile	FPGA makefile update.	2023-04-25 16:24:26 -05:00
probe	Added Jacob's ILA script.	2023-04-06 15:32:36 -05:00
wally.tcl	FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization.	2023-06-16 15:40:13 -05:00
wave_config.wcfg	Updated fpga wave configuration.	2022-11-16 15:57:19 -06:00
xlnx_ahblite_axi_bridge.tcl	Added more support for Arty A7 board.	2023-04-10 16:01:17 -05:00
xlnx_axi_clock_converter.tcl	Added more support for Arty A7 board.	2023-04-10 16:01:17 -05:00
xlnx_ddr3-artya7-mig.prj	It's almost working.	2023-04-18 14:24:59 -05:00
xlnx_ddr3-ArtyA7.tcl	Finally fixed the ddr3 mig script to work correclty.	2023-04-14 11:41:51 -05:00
xlnx_ddr4-vcu108.tcl	Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.	2022-10-24 15:38:39 -05:00
xlnx_ddr4-vcu118.tcl	Updated vcu118 constraints to run cpu at 38.43Mhz.	2022-11-15 10:19:38 -06:00
xlnx_ddr4.tcl	Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.	2022-10-24 15:38:39 -05:00
xlnx_mmcm.tcl	Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster.	2023-04-17 12:16:31 -05:00
xlnx_proc_sys_reset.tcl	Added more support for Arty A7 board.	2023-04-10 16:01:17 -05:00