415 Commits

Author	SHA1	Message	Date
Katherine Parry	59f79722ab	FDIV and FSQRT work	2021-07-21 14:08:14 -04:00
Katherine Parry	61f81bb76e	FMA parameterized	2021-07-20 22:04:21 -04:00
bbracker	d6c93a50aa	fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk	2021-07-20 17:55:44 -04:00
bbracker	b5ceb6f7c3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 15:04:13 -04:00
bbracker	945c8d496f	commented out old hack that used hardcoded addresses	2021-07-20 15:03:55 -04:00
David Harris	62b3673027	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 14:46:58 -04:00
David Harris	20744883df	flag for optional boottim	2021-07-20 14:46:37 -04:00
bbracker	7694342d4e	ignore mhpmcounters because QEMU doesn't implement them	2021-07-20 13:37:52 -04:00
bbracker	761300afcd	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 12:08:46 -04:00
David Harris	c117356432	Parameterized I$/D$ configurations and added sanity check assertions in testbench	2021-07-20 08:57:13 -04:00
bbracker	c9775de3b2	testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)	2021-07-20 05:40:39 -04:00
bbracker	5347a58192	major fixes to CSR checking	2021-07-20 00:22:07 -04:00
bbracker	aeaf4a31f0	MemRWM shouldn't factor into PCD checking	2021-07-19 18:03:30 -04:00
bbracker	5911029d2b	make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways	2021-07-19 17:11:42 -04:00
bbracker	009e9d97bf	adapt testbench to removal of ReadDataWEn signal	2021-07-19 15:42:14 -04:00
bbracker	02de6014b2	adapt testbench to removal of signal	2021-07-19 15:41:50 -04:00
bbracker	77b690faf0	make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset	2021-07-19 15:13:03 -04:00
Katherine Parry	8d101548f1	FDIV and FSQRT passes when simulating in modelsim	2021-07-18 23:00:04 -04:00
bbracker	f4f3ef0307	linux testbench progress	2021-07-18 18:47:40 -04:00
Katherine Parry	3527620c0b	fdivsqrt inegrated, but not completley working	2021-07-18 14:03:37 -04:00
Ross Thompson	a0017e39e2	Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue.	2021-07-17 21:02:24 -05:00
David Harris	c29a2ff8df	Started atomics	2021-07-17 21:11:41 -04:00
bbracker	6feb95c779	swapped out linux testbench signal names	2021-07-17 14:48:12 -04:00
David Harris	9741b01465	hptw: minor cleanup	2021-07-17 13:40:12 -04:00
David Harris	37cc2ca30f	hptw: factored pregen	2021-07-17 11:11:10 -04:00
David Harris	622a14cbdd	Removed more unused signals from ahblite	2021-07-17 02:21:54 -04:00
Kip Macsai-Goren	3d14d573a0	included virtual memory tests in testbench	2021-07-16 17:57:24 -04:00
Ross Thompson	965f34d78f	Added guide for Ben to do linux conversion.	2021-07-16 15:04:30 -05:00
Ross Thompson	abce241f68	Also changed the shadow ram's dcache copy widths. ... Merge branch 'dcache' into main	2021-07-16 14:21:09 -05:00
Ross Thompson	96aa106852	Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.	2021-07-15 11:56:35 -05:00
Ross Thompson	4549a9f1c9	Merge branch 'main' into dcache	2021-07-15 11:55:20 -05:00
Ross Thompson	c39a228266	Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.	2021-07-15 11:00:42 -05:00
Ross Thompson	f234875779	dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.	2021-07-14 23:08:07 -05:00
Ross Thompson	6163629204	Finally have the ptw correctly walking through the dcache to update the itlb. ... Still not working fully.	2021-07-14 22:26:07 -05:00
Katherine Parry	701ea38964	Fixed lint warning	2021-07-14 21:24:48 -04:00
Ross Thompson	d3a1a2c90a	Fixed d cache not honoring StallW for uncache writes and reads.	2021-07-14 17:23:28 -05:00
Ross Thompson	771c7ff130	Routed CommittedM and PendingInterruptM through the lsu arb.	2021-07-14 16:18:09 -05:00
Ross Thompson	278bbfbe3c	Partially working changes to support uncached memory access. Not sure what CommitedM is.	2021-07-13 17:24:59 -05:00
Katherine Parry	acdd2e4504	Fixed writting MStatus FS bits	2021-07-13 13:20:30 -04:00
Ross Thompson	d3ffbe0e5d	Modularized the shadow memory to reduce performance hit.	2021-07-13 10:55:57 -05:00
Ross Thompson	17dc488010	Got the shadow ram cache flush working.	2021-07-13 10:03:47 -05:00
Ross Thompson	9fe6190763	Team work on solving the dcache data inconsistency problem.	2021-07-12 23:46:32 -05:00
Ross Thompson	6b42b93886	Now updates the dtim with the dirty data in the dcache. ... Simulation is showing issues. It lookslike the cache is not evicting the correct data.	2021-07-12 15:13:27 -05:00
Ross Thompson	8ca8b9075d	Progress towards the test bench flush.	2021-07-12 14:22:13 -05:00
Katherine Parry	0cc07fda1b	Almost all convert instructions pass Imperas tests	2021-07-11 18:06:33 -04:00
bbracker	0e708a72f3	more completely uncomment MMU tests to make sim wally work	2021-07-06 14:33:52 -04:00
Kip Macsai-Goren	770420b448	added new mmu tests to makefrag and commented out in the testbench	2021-07-05 10:54:30 -04:00
David Harris	e65fb5bb35	Added F_SUPPORTED flag to disable floating point unit when not in MISA	2021-07-05 10:30:46 -04:00
David Harris	c897bef8cd	Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.	2021-07-04 01:19:38 -04:00
Ben Bracker	9709bd78e1	stop busybear from hanging	2021-07-02 17:22:09 -05:00