Lee Moore
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e1e693a1d2
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Merge pull request #13 from eroom1966/imperas
Merge pull request #5 from davidharrishmc/imperas
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2023-01-20 14:34:38 +00:00 |
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Lee Moore
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cddc111cd6
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Merge pull request #5 from davidharrishmc/imperas
Merge pull request #12 from eroom1966/imperas
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2023-01-20 14:33:21 +00:00 |
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Lee Moore
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56eeb7cf9b
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Merge pull request #12 from eroom1966/imperas
Imperas
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2023-01-20 14:32:57 +00:00 |
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Lee Moore
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3427f7de20
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Merge pull request #4 from davidharrishmc/imperas
Merge pull request #11 from eroom1966/imperas
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2023-01-20 14:32:21 +00:00 |
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eroom1966
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70f8c7a14e
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Merge branch 'imperas' of https://github.com/eroom1966/riscv-wally into imperas
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2023-01-20 14:31:17 +00:00 |
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Lee Moore
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fe4f8428ca
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Merge pull request #11 from eroom1966/imperas
Imperas
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2023-01-19 14:56:44 +00:00 |
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Lee Moore
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35a6e407b6
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Merge branch 'davidharrishmc:imperas' into imperas
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2023-01-19 14:56:18 +00:00 |
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eroom1966
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43d5769bd9
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update
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2023-01-19 13:29:46 +00:00 |
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eroom1966
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5212499513
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correct the HASH
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2023-01-19 10:41:11 +00:00 |
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Lee Moore
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e12867af8e
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Merge pull request #10 from eroom1966/imperas
Imperas
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2023-01-19 10:28:27 +00:00 |
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Lee Moore
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d12758675c
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Merge pull request #3 from davidharrishmc/imperas
Imperas
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2023-01-19 10:27:52 +00:00 |
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eroom1966
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f9b14ccdc5
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customer commands
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2023-01-19 10:20:55 +00:00 |
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Lee Moore
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2b07812051
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Merge pull request #9 from eroom1966/imperas
Partial fix for misaligned LD/ST
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2023-01-18 17:12:19 +00:00 |
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eroom1966
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8dea3491a3
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Partial fix for misaligned LD/ST
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2023-01-18 17:11:39 +00:00 |
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Lee Moore
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a032a9a174
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Merge pull request #8 from eroom1966/imperas
changes made with Ross
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2023-01-18 16:48:22 +00:00 |
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eroom1966
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0ccab9accc
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changes made with Ross
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2023-01-18 16:46:48 +00:00 |
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ross144
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786d7839ff
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Merge pull request #7 from eroom1966/imperas
Imperas
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2023-01-18 09:27:39 -06:00 |
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eroom1966
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247879e7c7
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add im flags for compressed disass
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2023-01-18 13:37:28 +00:00 |
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eroom1966
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52ebac59b8
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remove volatile for FFLAGS and FCSR
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2023-01-18 13:33:57 +00:00 |
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eroom1966
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68af12ece1
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refer to correct path
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2023-01-18 13:26:07 +00:00 |
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eroom1966
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7a4472f94e
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ignore external
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2023-01-18 13:22:32 +00:00 |
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eroom1966
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c120717027
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update for private copy of Imperas
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2023-01-18 13:19:14 +00:00 |
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Lee Moore
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2b43afba01
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Merge pull request #2 from davidharrishmc/imperas
Imperas
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2023-01-18 09:14:07 +00:00 |
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Ross Thompson
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374f95ebf3
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Fixed the rvvi CSR write enable not synchronized with a valid instruction in the Writeback stage.
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2023-01-17 18:24:46 -06:00 |
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ross144
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19230426d4
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Merge pull request #2 from eroom1966/imperas
Imperas
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2023-01-17 14:50:05 -06:00 |
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eroom1966
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cf3223df22
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refactor all rvvi into single initial block
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2023-01-17 13:01:01 +00:00 |
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eroom1966
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2ead2cdaf4
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Code refactor and addition of rvvi interface
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2023-01-17 12:47:38 +00:00 |
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Lee Moore
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485b041f02
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Merge pull request #1 from davidharrishmc/imperas
Imperas
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2023-01-17 09:23:41 +00:00 |
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Ross Thompson
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1680f89ef3
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Found a potential issue with mstatush when XLEN = 64.
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2023-01-16 13:57:28 -06:00 |
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Ross Thompson
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7984194c2a
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Fixed issue with rvvi tracer so it reports call csr changes, not just instrutions which write the CSRs.
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2023-01-16 13:35:06 -06:00 |
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Ross Thompson
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53c8042276
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Signal renames for ras.
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2023-01-13 15:56:10 -06:00 |
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Ross Thompson
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8e3e8591a6
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Removed 1 bit from instruction classification.
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2023-01-13 15:19:53 -06:00 |
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Ross Thompson
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37481fce77
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More branch predictor cleanup.
Found small bug. The decode stage was using the predicted instruction class rather than the decoded instruction class.
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2023-01-13 12:57:18 -06:00 |
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Ross Thompson
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b26cec1ef4
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Possible optimization of gshare.
I don't believe the Writeback stage ghr is needed.
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2023-01-13 12:39:29 -06:00 |
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Ross Thompson
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f7dacb59f9
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Possible minor enhancement to gshare.
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2023-01-13 12:32:39 -06:00 |
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Ross Thompson
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14ecaabbf6
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Nearly complete RVVI tracer.
Missing PMP registers and performance counters other than MCYCLE and MINSTRET.
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2023-01-12 18:43:39 -06:00 |
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Ross Thompson
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59b135d895
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Added supervisor mode registers to tracer.
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2023-01-12 17:04:41 -06:00 |
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Ross Thompson
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6500321aaf
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Added M CSRs to the CSRArray.
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2023-01-12 16:51:51 -06:00 |
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Ross Thompson
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8981739310
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added machine csr to logger.
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2023-01-12 16:35:19 -06:00 |
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Ross Thompson
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f3443e2eca
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Added support to print the gprs.
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2023-01-12 16:09:30 -06:00 |
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Ross Thompson
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0ea0e7a9e1
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rvvi trace is coming alone nicely.
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2023-01-12 14:46:31 -06:00 |
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Ross Thompson
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9a180f88f7
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Completely stripped down imperas simulation.
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
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2023-01-12 12:48:38 -06:00 |
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Ross Thompson
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5112ffcbc9
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Stripped out all signature checking.
Removed multiple tests loop.
Only runs 1 test now.
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2023-01-12 12:45:44 -06:00 |
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Ross Thompson
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8ee80c5d54
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Created separate imperas testbench.
Resolved logger issue with the duplicated instructions after commit.
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2023-01-12 12:07:07 -06:00 |
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Ross Thompson
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f59e1d03fc
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Added instruction logger.
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2023-01-12 10:09:34 -06:00 |
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Ross Thompson
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3a41854f2b
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Completed review of LSU.
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2023-01-11 19:06:03 -06:00 |
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Ross Thompson
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f15de26f5c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2023-01-11 18:52:49 -06:00 |
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Ross Thompson
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2f3bf9eaf5
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Improved LSU formating.
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2023-01-11 18:52:46 -06:00 |
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sarah-harris
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3b363f5f9d
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privilege unit -> privileged unit in ifu.sv
privilege unit -> privileged unit in ifu.sv
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2023-01-11 16:33:08 -08:00 |
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Ross Thompson
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0362e88098
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2023-01-11 17:26:11 -06:00 |
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