Ross Thompson
2f85ac7f38
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
...
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
2021-11-20 22:35:47 -06:00
slmnemo
870549c01a
Removed .* from hazard hzu(.*).
2021-11-17 14:21:23 -08:00
slmnemo
a98dcd11ee
Removed .* from hazard hzu(.*) in wallypipelinedhart.sv.
2021-11-17 14:08:08 -08:00
Noah Limpert
0ccc7d5fe8
ieu variable naming changed for clarity
2021-11-17 13:24:28 -08:00
Noah Limpert
832b23b8a4
Updated IFU variable naming for clarity
2021-11-17 12:39:05 -08:00
Kip Macsai-Goren
3f76549a7d
renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
2021-11-17 10:53:17 -08:00
Noah Limpert
21ea270fe2
Have replaced .* with signal names in ifu
2021-10-27 13:45:37 -07:00
David Harris
8b1dc81d34
more lsu/ifu lint cleanup
2021-10-23 12:00:32 -07:00
David Harris
b6bb33ecef
lint cleanup
2021-10-23 11:03:28 -07:00
David Harris
708b914a65
Lint cleanup from wallypipeliendhart
2021-10-23 10:29:52 -07:00
David Harris
817795f619
Lint cleanup: ahblite, ifu, hart
2021-10-23 10:12:33 -07:00
David Harris
24bb3f4baf
Added more pipeline stage suffixes to divider
2021-10-02 22:54:01 -04:00
David Harris
72c1cc33f5
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
Ross Thompson
bf312bb37c
Removed amo logic from ahblite. Removed many unused signals from ahblite.
2021-08-25 22:45:13 -05:00
Ross Thompson
bb3e94d68a
Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.
2021-08-23 15:46:17 -05:00
Ross Thompson
007812dbdc
Moved the ReadDataW register into the datapath.
...
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
2021-07-22 14:52:03 -05:00
Ross Thompson
ae2371f2ce
Added performance counters for dcache access and dcache miss.
2021-07-19 22:12:20 -05:00
David Harris
49ec45d04d
hptw: Removed NonBusTrapM from LSU
2021-07-17 15:22:24 -04:00
David Harris
e55546da34
hptw: Propagating PageTableEntryF removal through IFU
2021-07-17 15:04:39 -04:00
David Harris
bf56000f4e
hptw: Propagating PageTableEntryF removal through LSU
2021-07-17 15:01:01 -04:00
David Harris
fe8910437a
Replaced separate PageTypeF and PageTypeM with common PageType
2021-07-17 02:31:23 -04:00
David Harris
52fcc47cdf
Removed rest of HRDATAW from ahblite
2021-07-17 02:15:24 -04:00
Ross Thompson
4549a9f1c9
Merge branch 'main' into dcache
2021-07-15 11:55:20 -05:00
Ross Thompson
c954fb510b
Renamed DCacheStall to LSUStall in hart and hazard.
...
Added missing logic in lsu.
2021-07-15 10:16:16 -05:00
Katherine Parry
f8b76082e4
fpu unpacking unit created
2021-07-14 17:56:49 -04:00
Ross Thompson
e17de4eb11
Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.
...
This solves the committedM issue.
2021-07-14 15:00:33 -05:00
Ross Thompson
278bbfbe3c
Partially working changes to support uncached memory access. Not sure what CommitedM is.
2021-07-13 17:24:59 -05:00
Ross Thompson
ee09fa5f58
Moved StoreStall into the hazard unit instead of in the d cache.
2021-07-13 13:20:50 -05:00
Ross Thompson
2004b2e044
Fixed back to back store issue.
...
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
2021-07-13 12:46:20 -05:00
Katherine Parry
b9edbb15eb
Fixed writting MStatus FS bits
2021-07-13 13:22:04 -04:00
Katherine Parry
acdd2e4504
Fixed writting MStatus FS bits
2021-07-13 13:20:30 -04:00
David Harris
68d1f87101
Fixed InstrValid from W to M stage for CSR performance counters
2021-07-13 13:19:13 -04:00
Ross Thompson
6abd23a61d
Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.
...
Also faults and the dcache ptw interlock are not implemented.
2021-07-09 15:16:38 -05:00
Ross Thompson
d85bf23af3
Merged several of the load/store/instruction access faults inside the mmu.
...
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
2021-07-06 13:43:53 -05:00
David Harris
39fa84efdd
Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb
2021-07-04 18:56:30 -04:00
Ross Thompson
8e48865140
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 16:19:39 -05:00
Ross Thompson
8ae0a5bd7d
relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic.
2021-07-04 13:49:38 -05:00
David Harris
a5c0dc8c81
Fixed MPRV and MXR checks in TLB
2021-07-04 13:20:29 -04:00
David Harris
b5df9b282d
Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
2021-07-04 11:39:59 -04:00
Ross Thompson
9b959715a0
removed mmustall and finished port annotations on ptw and lsuArb.
2021-07-03 16:06:09 -05:00
Ross Thompson
fd088f8ecd
Added explicit names to lsu, lsuarb and pagetable walker to make the code refactoring process eaiser.
2021-07-03 15:51:25 -05:00
Ross Thompson
46831035fb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-02 13:56:49 -05:00
Ross Thompson
549b7b2a62
Merge branch 'main' into bigbadbranch
2021-07-02 11:52:26 -05:00
David Harris
1ce98cc100
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-02 12:52:20 -04:00
David Harris
648c09e5ef
Optimized PMP checker logic and added support for configurable number of PMP registers
2021-07-02 11:04:13 -04:00
Ross Thompson
386193de00
added page table walker fault exit for icache.
2021-07-01 17:59:55 -05:00
Ross Thompson
b31e0afc2a
The icache now correctly interlocks with the PTW on TLB miss.
2021-06-30 11:24:26 -05:00
Ross Thompson
2598f08782
Page table walker now walks the table.
...
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
2021-06-29 22:33:57 -05:00
Katherine Parry
6216bd7172
FPU control signals changed and FMA works
2021-06-28 18:53:58 -04:00
Ross Thompson
ae6140bd94
Don't use this branch walker still broken.
2021-06-28 17:26:11 -05:00
