12 Commits

Author	SHA1	Message	Date
David Harris	2580d37fc0	ZK cleanup, check no LLEN > XLEN without D$, add half and quad float load/store to instruction name decoder	2024-03-10 22:03:57 -07:00
David Harris	efdc571f59	Removed redundant assertion	2024-02-01 20:14:40 -08:00
David Harris	49714cb282	Fixed assertions to throw fatal error, improved nightly regression to have passing cases	2024-01-31 21:39:18 -08:00
Rose Thompson	408bb2c35b	Yay! I got verilator to compile our testbench! Does it actually work I don't know.	2023-12-18 16:44:34 -06:00
David Harris	28752303be	Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there	2023-10-04 12:28:12 -07:00
David Harris	c6631ef808	Added N and PBMT bits to MMU PTE	2023-08-24 19:44:46 -07:00
David Harris	001d3cfdc5	Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder	2023-07-02 13:29:27 -07:00
David Harris	c2913f49a3	Added assertions for ZICNTR and ZIHPM	2023-06-16 09:26:02 -07:00
Ross Thompson	b8a243827b	Found a whole bunch of files still using the old `define configurations.	2023-06-15 13:09:07 -05:00
David Harris	3678ab556c	Removed unneeded diagnostic print	2023-03-03 16:46:16 -08:00
David Harris	cf8b5f0783	Added support for ZMMUL	2023-02-27 07:29:53 -08:00
David Harris	9d83749ca6	moved riscvassertons to its own file, added proper license headers to testbench support files	2023-02-16 19:40:27 -08:00