57 Commits

Author	SHA1	Message	Date
David Harris	da4eca4854	Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int.	2024-01-15 13:24:57 -08:00
David Harris	9eb6d9c8b8	Added Zicond support	2024-01-11 07:37:15 -08:00
David Harris	dc3284049c	Rolled back B extension in rv32/64gc MISA because imperasDV isn't matching	2023-12-21 11:03:50 -08:00
David Harris	09ea6e6485	Set B in MISA for rv32gc and rv64gc	2023-12-20 16:29:31 -08:00
Rose Thompson	5062a8c89c	Added parameter for cache's SRAM length. ... Progress towards verilator support.	2023-12-18 12:50:49 -06:00
David Harris	b692c913c4	Changed rv32gc to do IDIV in MDU and have k=2 copies of FDIV stages; added correct sky130 adder data; fixed feature substitution in synthesis makefile	2023-11-18 20:56:50 -08:00
David Harris	acc2db256f	turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep	2023-11-17 20:25:24 -08:00
Rose Thompson	fdb75203cb	Added cbop to to rv32gc.	2023-11-14 10:55:22 -06:00
Rose Thompson	95fc5f4a1c	Towards removing the FPGA config file.	2023-11-13 17:20:26 -06:00
Rose Thompson	b74bfbeefd	Merge branch 'main' into Zicclsm	2023-11-10 16:15:32 -06:00
Rose Thompson	657409aec5	Addec ZICCLSM to config files and started on lsu instance.	2023-10-27 13:07:23 -05:00
naichewa	0ff9ce527d	Merge branch 'main' into spi	2023-10-16 22:59:50 -07:00
David Harris	1a6e57f8c0	Renamed wally-config to config in many comments	2023-10-16 13:49:09 -07:00
naichewa	d5d4f9d044	transferred spi changes in ECA-authorized commit	2023-10-12 13:36:57 -07:00
David Harris	28752303be	Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there	2023-10-04 12:28:12 -07:00
Ross Thompson	f863cbf366	Actually fixed non-power of 2 issue with RAS. ... Added RAS swapping to branch predictor scripts and configurations.	2023-09-27 12:25:05 -05:00
Ross Thompson	95c653e7df	Fixes the bpred-sim.py to support command line parameterization of the branch predictor while using the new parameterization. This is definitely a hack, but I don't see a better way.	2023-09-15 14:05:26 -05:00
David Harris	7a092a2275	Fixed merge conflict for ZICBOP	2023-08-25 18:41:57 -07:00
David Harris	c6631ef808	Added N and PBMT bits to MMU PTE	2023-08-24 19:44:46 -07:00
Ross Thompson	914b6f9734	Now have CBOZ instructions working!	2023-08-24 16:47:35 -05:00
Ross Thompson	0662df511d	Modified rv32gc and rv64gc configs to enabled Zicbom.	2023-08-21 13:48:20 -05:00
David Harris	d58ece3d44	renamed test-shared.vh to config-shared.vh	2023-07-30 05:22:39 -07:00
Ross Thompson	0ae9e8bfde	Removed old sdc from all configs.	2023-07-24 15:55:22 -05:00
Ross Thompson	a89a1e675c	Merge branch 'boot' into mergeBoot ... Merges Jacob's new sdc controller into wally.	2023-07-21 17:43:45 -05:00
Ross Thompson	af0e33209f	Removed QEMU from configurations.	2023-07-19 10:23:55 -05:00
Ross Thompson	b756b248b4	Wow. The newest version of Vivado does not like the enums as parameters. ... The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.	2023-07-18 15:07:10 -05:00
David Harris	644afa16cd	Clean up privilege rs1 decoding and implement svinval as sfence.vma	2023-07-13 02:41:17 -07:00
Ross Thompson	85567841eb	Merge branch 'testbench-params2'	2023-06-15 15:31:13 -05:00
Ross Thompson	87fb9a3e16	Deleted remaining old configs except fpga as I still need to create the parameterized version.	2023-06-15 14:08:13 -05:00
Ross Thompson	c7536663c0	Merge pull request #319 from davidharrishmc/dev ... Renamed Performance Counter extension	2023-06-09 21:21:45 -04:00
David Harris	b70b0c7c5e	Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare	2023-06-09 14:40:01 -07:00
David Harris	df96900aa1	Added named support for Zicntr and Zihpm	2023-06-09 09:35:51 -07:00
Ross Thompson	a8a8422557	Updated parameterization types. Modelsim version 2022.1 did requires defaults to a 32 bit integer. The base and ranges for the address decoder need to be larger.	2023-06-09 09:28:24 -05:00
Ross Thompson	1315a0bf4a	Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check.	2023-05-26 16:00:14 -05:00
Ross Thompson	0020d94b39	Updated mmu's tlb and hptw to use Lim's parameterization.	2023-05-24 18:02:22 -05:00
Ross Thompson	930fb67308	Trying to figure out why the parameterization slowed down modelsim so much.	2023-05-24 12:44:42 -05:00
Ross Thompson	69a9bf7055	Adds local history predictor. ... Fixes performance counters, but not coremark.	2023-05-23 18:53:46 -05:00
Ross Thompson	d545a2ec74	Partially working local history repair.	2023-05-11 14:56:26 -05:00
Ross Thompson	414c79b923	Updated configs for local branch history `defines.	2023-05-02 11:11:04 -05:00
Kip Macsai-Goren	4aed880757	enabled SVADU for rv32/64gc	2023-04-11 17:42:26 -07:00
kipmacsaigoren	2337e2ae16	Merge branch 'openhwgroup:main' into bit-manip	2023-03-07 21:29:03 -08:00
Kip Macsai-Goren	75f6e9eb34	added S time compare to gc configs	2023-03-04 15:46:26 -08:00
Kip Macsai-Goren	6be322941d	Merge remote-tracking branch 'upstream/main' into bit-manip	2023-03-03 09:36:44 -08:00
Ross Thompson	b98e007a53	Cleaned up branch predictor performance counters.	2023-03-01 17:05:42 -06:00
Kip Macsai-Goren	58ab6ec805	Merge remote-tracking branch 'upstream/main' into bit-manip	2023-02-28 14:41:51 -08:00
David Harris	cf8b5f0783	Added support for ZMMUL	2023-02-27 07:29:53 -08:00
David Harris	35653a18b7	Renamed HPTW_WRITES_SUPPORTED to SVADU_SUPPORTED	2023-02-26 09:38:32 -08:00
Kip Macsai-Goren	1a9ba9d944	added 32 bit tests for bit manipulation	2023-02-22 20:17:52 -08:00
Ross Thompson	7df3a84060	Renamed branch predictors and consolidated global and gshare predictors.	2023-02-20 18:42:37 -06:00
David Harris	36b2d530c4	Merge pull request #98 from ross144/main ... New gshare implementation	2023-02-20 11:27:47 -08:00