Ross Thompson
b05abc1795
cleanup.
2022-01-31 13:29:04 -06:00
Ross Thompson
d2ab17e1af
Repaired linux-wave.do
2022-01-31 12:54:18 -06:00
Ross Thompson
3475e142a5
Repaired wavefile and fixed modelsim warning.
2022-01-31 12:34:17 -06:00
Ross Thompson
fa8914a830
Cleanup busdp.
2022-01-31 12:17:07 -06:00
Ross Thompson
7c3d6bbdb4
Moved lsu virtual memory logic into separate module.
2022-01-31 11:56:03 -06:00
Ross Thompson
e35a8299ec
Encapsulated dtim.
2022-01-31 11:23:55 -06:00
Ross Thompson
dbe40856a2
Removed unused signals in the LSU.
2022-01-31 10:35:35 -06:00
Ross Thompson
bfbc31d184
Moved atomic logic to own module.
2022-01-31 10:28:12 -06:00
Ross Thompson
ef770fd183
Encapsulated the bus data path into a separate module.
2022-01-31 10:15:48 -06:00
Ross Thompson
d52c5b0393
LSU and IFU cleanup.
2022-01-28 15:26:06 -06:00
Ross Thompson
147d71fd46
Clean up of mmu instances in IFU and LSU.
2022-01-28 14:02:05 -06:00
Ross Thompson
1bb8d36308
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
Ross Thompson
d7d7c1cb7d
Relocated the misalignment faults.
2022-01-27 16:03:00 -06:00
David Harris
62e5c7fd13
Comments in LSU code about restructuring
2022-01-27 15:53:59 +00:00
Ross Thompson
23c4ba2777
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
David Harris
22c84dcd80
simpleram simplification
2022-01-25 19:46:13 +00:00
David Harris
f07123ff0f
simpleram simplification
2022-01-25 18:26:31 +00:00
David Harris
5eb71a3bbe
simpleram address simplification
2022-01-25 18:00:50 +00:00
David Harris
d9888c91a6
simpleram clk and reset simplification
2022-01-25 17:34:15 +00:00
Ross Thompson
4ecc2d029a
Changed the IROM and DTIM memories to behave like edge-triggered srams.
2022-01-21 15:42:54 -06:00
David Harris
ca1f7ce5d3
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
David Harris
8b62130070
lsu cleanup down to 346 lines
2022-01-15 01:19:44 +00:00
David Harris
b967bcede2
LSU Cleanup
2022-01-15 01:11:17 +00:00
David Harris
f7f3882cb8
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
David Harris
d9e8d16bbe
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
David Harris
b0263012e8
LSU cleanup
2022-01-15 00:11:30 +00:00
David Harris
4c5962095e
LSU cleanup
2022-01-15 00:03:03 +00:00
David Harris
37bf5347cf
LSU cleanup
2022-01-14 23:55:27 +00:00
David Harris
380e990def
moved fp to tests
2022-01-14 23:05:59 +00:00
David Harris
291deb5c39
LSU partitioning
2022-01-14 23:02:28 +00:00
Ross Thompson
5726b5b640
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
Ross Thompson
9f7e3f147b
Partial local dtim in lsu configuration.
2022-01-13 17:50:31 -06:00
Ross Thompson
0b06fa12ef
Merge branch 'testDivInterruptInterlock' into main
2022-01-13 11:21:48 -06:00
Ross Thompson
4bcabd1a55
Removed unused inputs to hptw.
2022-01-13 11:04:48 -06:00
Ross Thompson
654a33bf92
Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu.
2022-01-12 17:41:39 -06:00
Ross Thompson
26fb09c868
Added additional fsm to ILA.
2022-01-12 14:17:16 -06:00
Ross Thompson
6eb2f37ce4
Possible fix for the TrapM DTLBMiss suppression.
2022-01-12 14:17:16 -06:00
Ross Thompson
6b483e621d
If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.
...
This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
2022-01-12 14:17:16 -06:00
Ross Thompson
55456e465c
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
b6ae6fea27
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
...
only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
3d2671a8b0
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
Ross Thompson
de3bbd3fe0
Also fixed undetected bug with amo concurrent with tlb miss. It was possible for the amoalu to apply a function to the hptw readdata.
...
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 23:28:02 -06:00
Ross Thompson
fa0080ca70
Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
...
assign from the input non translated virtual address. Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address. This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
David Harris
2df92af488
Capitalized LSU and IFU, changed MulDiv to MDU
2022-01-07 04:30:00 +00:00
Ross Thompson
e74e8c2e86
Changed names of address in caches.
...
Removed old cache files.
2022-01-05 22:19:36 -06:00
Ross Thompson
1ab3a17ff7
Updates to support fpga.
2022-01-05 18:07:23 -06:00
David Harris
6d4714651c
Removed more generate statements
2022-01-05 16:25:08 +00:00
David Harris
d66f7c841b
Removed generate statements
2022-01-05 14:35:25 +00:00
Ross Thompson
98be8201b2
Renamed most signals inside cache.sv so they are agnostic to i or d.
2022-01-04 23:52:42 -06:00
Ross Thompson
fffaf654e6
the i and d caches now share common verilog.
2022-01-04 23:40:37 -06:00
Ross Thompson
13dbf3cc0f
parameterized the caches with the goal of using common rtl for both i and d caches.
2022-01-04 22:40:51 -06:00
Ross Thompson
888a60d8d6
Switched block for line in caches.
2022-01-04 22:08:18 -06:00
David Harris
d1a7416028
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-04 19:47:51 +00:00
David Harris
115287adc8
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
