12 Commits

Author	SHA1	Message	Date
Ross Thompson	d77adbd673	Signal name cleanup.	2022-03-10 18:26:58 -06:00
Ross Thompson	50789f9ddd	Byte write enables are passing all configs now.	2022-03-10 17:26:32 -06:00
David Harris	3e16730226	RAM simplification	2022-02-08 20:15:23 +00:00
Ross Thompson	23c4ba2777	1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU. ... 2. Removed the write address delay from simpleram.sv 3. Fixed rv32tim and rv32ic mode to handle missalignment correctly. 4. Added imperas32i and imperas32c to rv32tim mode.	2022-01-26 18:23:39 -06:00
David Harris	8bf73d0eb3	simpleram simplification	2022-01-25 19:40:07 +00:00
David Harris	f07123ff0f	simpleram simplification	2022-01-25 18:26:31 +00:00
David Harris	7ac44cb3fc	simpleram address simplification	2022-01-25 18:17:33 +00:00
David Harris	5eb71a3bbe	simpleram address simplification	2022-01-25 18:00:50 +00:00
David Harris	d9888c91a6	simpleram clk and reset simplification	2022-01-25 17:34:15 +00:00
Ross Thompson	4ecc2d029a	Changed the IROM and DTIM memories to behave like edge-triggered srams.	2022-01-21 15:42:54 -06:00
David Harris	ca1f7ce5d3	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
Ross Thompson	5726b5b640	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00