Ross Thompson
d430659983
fixed the read timer issue but we still have problems with interrupts and i/o devices.
2021-08-06 10:16:06 -05:00
David Harris
c117356432
Parameterized I$/D$ configurations and added sanity check assertions in testbench
2021-07-20 08:57:13 -04:00
David Harris
b2f7952b3d
Added cache configuration to config files
2021-07-19 18:19:46 -04:00
David Harris
8ca7abaa02
Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0
2021-07-05 20:35:31 -04:00
David Harris
6b9cfe90d8
Added ASID & Global PTE handling to TLB CAM
2021-07-04 17:52:00 -04:00
David Harris
c897bef8cd
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 01:19:38 -04:00
Ross Thompson
549b7b2a62
Merge branch 'main' into bigbadbranch
2021-07-02 11:52:26 -05:00
Ross Thompson
17636b3293
Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults.
2021-06-25 11:05:17 -05:00
Ross Thompson
0377d3b2c9
Progress.
2021-06-24 13:05:22 -05:00
bbracker
83a1f29c37
remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
2021-06-20 22:38:25 -04:00
David Harris
72d8d34e3c
allow all size memory access in CLINT; added underscore to peripheral address symbols
2021-06-18 08:05:50 -04:00
David Harris
91a13999a9
Added SUPPORTED to each peripheral in each config file
2021-06-17 21:36:32 -04:00
bbracker
f0266f621b
merge
2021-06-10 10:03:01 -04:00
bbracker
31e1c926f2
attempt to fix regression by adding PMP_ENTRIES to configs
2021-06-10 09:59:26 -04:00
David Harris
e231fc6b00
More verilator fixes, but bpred is broken
2021-06-09 21:03:03 -04:00
Kip Macsai-Goren
fcb9b1f0e1
working version with new mmu comments, old boottim values
2021-06-08 15:20:25 -04:00
David Harris
cfe5c27946
Resized BOOT TIM to 1 KB
2021-06-08 14:04:32 -04:00
David Harris
b37bcc8e38
Continued merge
2021-06-07 12:49:47 -04:00
David Harris
1e67db2f0c
Second attept to commit refactoring config files
2021-06-07 12:37:46 -04:00
David Harris
95cc70295b
Merge difficulties
2021-06-07 09:50:23 -04:00
David Harris
8bbabb683d
Refactored configuration files and renamed testbench-busybear to testbench-linux
2021-06-07 09:46:52 -04:00
Kip Macsai-Goren
b99b5f8e0e
moved privilege dfinitions into wally-constants, upgraded relevant includes
2021-06-04 17:55:07 -04:00
David Harris
b836679ae1
Started MMU
2021-06-04 11:59:14 -04:00
Ross Thompson
14a69c1d06
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Ross Thompson
44d28dbd1c
Icache integrated!
...
Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
Ross Thompson
9e40fb072c
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
bbracker
5687ab1c96
do script refactor
2021-04-24 09:32:09 -04:00
Noah Boorstin
c7a09d2359
yay buildroot passes a decent amount of tests now
...
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
2021-04-19 03:26:08 -04:00
Noah Boorstin
5902637632
buildroot: sim is now running!
...
yes it only gets through 5 instructions right now. Yes that's my fault.
2021-04-17 14:44:32 -04:00
Noah Boorstin
541fb22dc9
start to add buildroot testbench
...
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
2021-04-16 23:27:29 -04:00
Domenico Ottolia
a149f2f3d8
Add support for vectored interrupts
2021-04-15 19:13:42 -04:00
bbracker
ce7b2314ef
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 06:40:53 -04:00
Ross Thompson
e6aef66853
Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses.
2021-03-23 13:54:59 -05:00
Noah Boorstin
4be19421c4
busybear: allow overwriting read values
2021-03-22 17:28:44 -04:00
bbracker
eea7e2e47e
first pass at PLIC interface
2021-03-22 10:14:21 -04:00
Shreya Sanghai
dfc86539cc
Merge branch 'gshare' into main
...
Conflicts:
wally-pipelined/regression/wave.do
2021-03-18 17:25:48 -04:00
Ross Thompson
9386e6a524
Switched to gshare from global history.
...
Fixed a few minor bugs.
2021-03-18 16:05:59 -05:00
Noah Boorstin
847bf0b9a6
change ifndef to generate/if
2021-03-18 12:50:19 -04:00
Noah Boorstin
a226e24ed3
busybear: update memory map, add GPIO
2021-03-18 12:17:35 -04:00
Noah Boorstin
162955de69
busybear: add COUNTERS define
2021-03-16 21:08:47 -04:00
Shreya Sanghai
d9b1e7d67f
added gshare and global history predictor
2021-03-16 17:03:01 -04:00
Shreya Sanghai
a79e26f9d8
added global history branch predictor
2021-03-16 16:06:40 -04:00
Ross Thompson
8e51935082
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
2021-03-15 12:39:44 -05:00
Noah Boorstin
0af002eb2f
busybear: make CSRs only weird for us
2021-03-05 00:46:32 +00:00
Noah Boorstin
f11b3108d8
busybear: fix bootram range
2021-03-01 17:45:21 +00:00
Noah Boorstin
2769b147cb
busybear: add 2nd dtim for bootram
2021-02-28 16:08:54 +00:00
Noah Boorstin
969c094489
busybear: remove gpio, start adding 2nd ram
2021-02-28 06:02:40 +00:00
Noah Boorstin
cca60ed06d
update busybear testbench to conform to new structure
...
aaaaaaaaaaaaaaaaaahhhh so many changes
also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
2021-01-30 19:19:00 +00:00
Noah Boorstin
7183910c84
update busybear testbench to conform to new structure
2021-01-29 17:46:50 +00:00
Noah Boorstin
0fa7cffb11
busybear: lie about MISA to match OVP's MISA
2021-01-29 00:58:56 -05:00
