136 Commits

Author	SHA1	Message	Date
David Harris	9e2c3bef3c	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-12-08 13:48:49 -08:00
Noah Limpert	e97dd080a0	updated fcmp.sv instantiation to remove x*'s	2021-12-08 13:34:33 -08:00
David Harris	a174c8b4d7	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-12-08 12:33:59 -08:00
David Harris	5d4014d351	Refactoring ALU and datapath muxes	2021-12-08 12:33:53 -08:00
Katherine Parry	d0e708f239	FMA uses one LOA	2021-12-07 14:15:43 -08:00
Ross Thompson	e43aa6ead4	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
David Harris	4b57af9cff	PIPELINE test running	2021-11-01 12:44:35 -07:00
David Harris	9cfb8deaab	Fixed FResultSelM to select proper flags	2021-10-27 11:02:42 -07:00
David Harris	44de52a05a	Synchronous reset in non-flop blocks	2021-10-26 08:30:35 -07:00
David Harris	d0aa6911ff	random lint cleanup	2021-10-23 11:24:36 -07:00
David Harris	bb4ad264ce	IEU cleanup	2021-10-23 11:13:28 -07:00
David Harris	2abec36221	Lint cleanup	2021-10-23 09:58:52 -07:00
David Harris	6ae9aa7d80	lint cleanup: FPU and privileged	2021-10-23 09:41:24 -07:00
David Harris	0eabd0ecc2	FMA and CSRC lint cleanup	2021-10-23 09:20:24 -07:00
David Harris	5235e61d9e	Lint cleanup	2021-10-23 09:06:21 -07:00
David Harris	8b854bb1c2	Cleaned up LINT erors	2021-10-23 06:28:49 -07:00
David Harris	5142bfd624	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-23 06:15:49 -07:00
David Harris	3407b63c8a	Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.	2021-10-23 06:15:26 -07:00
Ross Thompson	6bad4058eb	Merge branch 'main' into fpga	2021-10-22 16:09:16 -05:00
James E. Stine	a60e19dc3f	Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking	2021-10-22 13:41:50 -05:00
Katherine Parry	00cc1e0c5c	put the FMA priority encoders into their own module	2021-10-22 10:03:12 -07:00
James E. Stine	0e0a107a98	Get rid of lint warning - still need more testing though	2021-10-21 15:19:22 -05:00
James E. Stine	49721a169b	Clean up some FPU and add pipelined fpdivsqrt to fpu.sv	2021-10-21 13:52:12 -05:00
James E. Stine	129ef03b2d	Fix fpdivsqrt lint error on CPA for convergence	2021-10-20 17:46:13 -05:00
Ross Thompson	09dc3e1143	Merge branch 'main' into fpga	2021-10-20 16:24:55 -05:00
James E. Stine	7536e0a2ee	Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.	2021-10-20 12:00:41 -05:00
Katherine Parry	33e5a078bf	cvtfp module documented	2021-10-14 15:25:31 -07:00
James E. Stine	6b30adb309	Clean up some signals - beautification onging	2021-10-14 17:12:00 -05:00
James E. Stine	eb64a7f0c9	Update to fpdivsqrt to go on posedge as it should. Also an update to ... individual regression test for TestFloat (still needs some tweaking)	2021-10-13 17:14:42 -05:00
Katherine Parry	09f51871c5	lint warnings fixed	2021-10-12 09:45:02 -07:00
Katherine Parry	4ea56ac68b	some fpu lint warnings fixed - still working on it	2021-10-11 18:32:03 -07:00
Ross Thompson	5fdac9fa3b	Merge branch 'main' into fpga	2021-10-11 18:17:58 -05:00
bbracker	8eff03bf1a	simplify flopenrc's that didn't actually need to be flopenrc's	2021-10-10 12:25:05 -07:00
Katherine Parry	44b023ace1	FMA matches diagram and lint warnings fixed	2021-10-09 17:38:10 -07:00
kipmacsaigoren	086e6d130a	rename adder in fpu for synthesis	2021-10-08 17:47:54 -05:00
James E. Stine	b90d7b8083	Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat	2021-10-06 08:26:09 -05:00
Ross Thompson	d4f514010d	Changes to make fpga synthesizable. ... Added preload to test simple program on wally in fpga.	2021-09-22 10:54:13 -05:00
David Harris	1f6e4c71fc	Modified rxfull determination in UART, started division	2021-09-12 20:00:24 -04:00
Ross Thompson	3b12235954	Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches.	2021-09-11 15:40:27 -05:00
Katherine Parry	7607adc951	FMA cleanup	2021-08-28 10:53:35 -04:00
Katherine Parry	facd4062d0	all conversions go through the execute stage result mux	2021-08-16 13:06:09 -04:00
Katherine Parry	567260751a	move some FPU select muxs to execute stage	2021-08-13 14:41:22 -04:00
Katherine Parry	21555c392f	LZA added to FMA and attemting a merged FMA and adder in synthesis	2021-08-10 13:57:16 -04:00
Katherine Parry	d8ca70fc45	all fpu units use the unpacking unit	2021-07-28 23:49:21 -04:00
Katherine Parry	8198e8162a	fixed some fpu lint errors	2021-07-24 16:41:12 -04:00
Katherine Parry	85d240c2a5	fpu cleanup	2021-07-24 15:00:56 -04:00
Katherine Parry	67ab0b165c	fpu cleanup	2021-07-24 14:59:57 -04:00
David Harris	427063ee05	Minor unpacking cleanup	2021-07-22 17:52:37 -04:00
David Harris	0822d46e97	Move Z sign swapping out of unpacker	2021-07-22 14:32:38 -04:00
David Harris	85aaa4c6d7	Move Z=0 mux out of unpacker.	2021-07-22 14:28:55 -04:00