Ross Thompson
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c3b77926d5
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I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
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2022-12-18 18:30:35 -06:00 |
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Ross Thompson
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e8c1d14abb
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Have a basic cache test to fill all ways and sets.
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2022-12-18 17:20:30 -06:00 |
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Ross Thompson
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7a352edf13
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Attempted to make a cache test.
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2022-12-18 17:15:08 -06:00 |
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Ross Thompson
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9d1cb9337e
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Updated tests for fpga and BP.
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2022-12-18 16:24:26 -06:00 |
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David Harris
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643a2e7cf9
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Use FPU divider for integer division when F is supported
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2022-12-14 17:03:13 -08:00 |
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Kip Macsai-Goren
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55627f40e2
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added passing GPIO test to 64 bit tests
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2022-12-05 21:31:00 -08:00 |
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Kip Macsai-Goren
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4c81b6fa5f
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added corrrect scr read out of uart to periph test
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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4ab99904a4
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added all 32 bit tests to 64 bit periph tests except gpio
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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51e78d9e48
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added copies of 64 bit tests to 32 bit periph and priv tests
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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540d6c2f41
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added -01 to all WALLY tests
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2022-12-05 20:16:02 -08:00 |
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Ross Thompson
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fc05e27416
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Updated riscv arch test removed misaligned1.
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2022-12-04 00:18:10 +00:00 |
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Kip Macsai-Goren
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9b1765ce92
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added tests for invalid address being written to satp. Not passing regression
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2022-11-27 13:22:35 -08:00 |
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Kip Macsai-Goren
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21e045eb7d
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added potential fix to overrun error and fifo interrupt error. test passes
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2022-11-06 22:01:02 -08:00 |
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Kip Macsai-Goren
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90ef371abc
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fixed fifo timout handling. error now in data ready interrupt
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2022-11-05 13:34:24 -07:00 |
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Kip Macsai-Goren
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c06da6e6fe
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fixed broken instructions so make works.
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2022-11-03 23:06:20 +00:00 |
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Ross Thompson
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f1eb20ef4d
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Updated to put dtb into the rodata segment for our linker script.
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2022-11-03 17:48:20 -05:00 |
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Ross Thompson
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1d7002e5c5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-03 17:36:04 -05:00 |
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Ross Thompson
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ccce0df535
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Potentially a valid zero stage boot loader based on cva6.
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2022-11-03 17:35:57 -05:00 |
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Ross Thompson
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103514a8e0
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More outline for uart timeout interrupt.
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2022-10-28 13:53:56 -05:00 |
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Ross Thompson
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21eca47d2e
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Untested change to uart test for outline of how to handle rx fifo timeout.
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2022-10-28 13:31:16 -05:00 |
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Kip Macsai-Goren
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6e45698b86
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Added test for UART FIFO timeout. Does not pass regression
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2022-10-25 05:35:56 +00:00 |
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Ross Thompson
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a59df0c77d
|
Created one off test to replicate the floating point forwarding hazard bug.
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2022-10-22 16:29:12 -05:00 |
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Kip Macsai-Goren
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c18c181fc0
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fixed endianness mstatush problem, passes make, not regression
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2022-10-04 17:37:39 +00:00 |
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Kip Macsai-Goren
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e603973dff
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added xlen and endianness test edits. xlen passes but endinanness still won't make
|
2022-09-26 05:03:19 +00:00 |
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Kip Macsai-Goren
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9821a50eaa
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added mstatus uxl, sxl bit tests (not tested in regression yet)
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2022-09-18 00:11:29 +00:00 |
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Kip Macsai-Goren
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0cc7f5719c
|
ported endianness tests to 32 bits (not tested in regression yet)
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2022-09-18 00:10:29 +00:00 |
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Kip Macsai-Goren
|
c5cbe43732
|
Fixed typos in existing endianness test
|
2022-09-18 00:09:52 +00:00 |
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Kip Macsai-Goren
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e6987524ab
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added full coverage of subword loads and stores to endianness test
|
2022-09-17 23:14:38 +00:00 |
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Kip Macsai-Goren
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cc7d1c8ef9
|
Created initial endianness tests
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2022-09-16 01:06:26 +00:00 |
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David Harris
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898dbc8e74
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Completed PLIC-S tests. Regression working. This completes peripheral tests.
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2022-08-03 09:33:56 -07:00 |
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David Harris
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4fb467ee8a
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Debugging plic-s test
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2022-08-03 13:21:09 +00:00 |
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David Harris
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7e5b78f240
|
plic-s debug
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2022-08-03 12:33:09 +00:00 |
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David Harris
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cab0349701
|
Started plic-s tests
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2022-08-03 03:48:08 +00:00 |
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David Harris
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93d7d7179e
|
Added parity and stop bit tests to UART
|
2022-07-28 04:35:51 +00:00 |
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David Harris
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429bdae1c4
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Fixed UART reference output
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2022-07-27 22:16:38 +00:00 |
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David Harris
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b08c87cb47
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Finished UART test
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2022-07-27 04:06:59 +00:00 |
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David Harris
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75a265159b
|
Increased timeout threshold to avoid timeout building riscof tests on slow machine
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2022-07-27 04:05:21 +00:00 |
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slmnemo
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7348af7fd5
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Updated reference file for UART test
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2022-07-26 09:39:31 -07:00 |
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slmnemo
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a9d5805990
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-26 09:15:20 -07:00 |
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slmnemo
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5218865a7f
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Committing changes made to UART test
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2022-07-26 09:14:40 -07:00 |
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David Harris
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2d7f4b133c
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More work toward riscof tests
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2022-07-26 06:19:13 -07:00 |
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David Harris
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c6a58eb5b6
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Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd
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2022-07-25 16:23:10 -07:00 |
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David Harris
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416f5edfe0
|
More riscof makefile tuning
|
2022-07-25 21:15:56 +00:00 |
|
David Harris
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7f7b3359b0
|
Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings
|
2022-07-25 20:50:38 +00:00 |
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slmnemo
|
bfced6bfe8
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-22 17:13:38 -07:00 |
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slmnemo
|
ca4511b6dc
|
Fixed UART FIFO bugs and added FIFO tests
|
2022-07-22 17:13:19 -07:00 |
|
Daniel Torres
|
d0aaae26fe
|
fixed wally rv32e tests, updated regression makefile to new testflow
|
2022-07-22 17:09:46 -07:00 |
|
Daniel Torres
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4da96c5791
|
fixed 32priv tests, now passing
|
2022-07-22 15:35:20 -07:00 |
|
Daniel Torres
|
24828db612
|
changes to test.vh for compatability
|
2022-07-22 15:00:48 -07:00 |
|
Daniel Torres
|
4198145ce2
|
added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
|
2022-07-22 14:58:55 -07:00 |
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