235 Commits

Author	SHA1	Message	Date
David Harris	653c458241	Moved fpu modules into subdirectories	2022-09-20 04:12:05 -07:00
David Harris	59b6346a28	Removed unused otfc for Q	2022-09-19 00:43:27 -07:00
Ross Thompson	cea012a640	renamed multimanager to multicontroller.	2022-09-14 14:03:37 -05:00
Ross Thompson	c7d3580637	Renamed signals in the LSU.	2022-09-13 11:47:39 -05:00
David Harris	c730ddf74a	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-09-07 11:11:39 -07:00
David Harris	7a29f9c95b	Running 16-bit square root cases first in testfloat	2022-09-07 11:11:35 -07:00
Ross Thompson	0615798467	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-09-07 12:26:50 -05:00
Ross Thompson	83306ec238	Named change for ahb tests to be less annoying.	2022-09-07 12:24:41 -05:00
Ross Thompson	3571fb18c2	Modified regression tests to add some ahb configurations.	2022-09-07 12:03:58 -05:00
David Harris	dff9416a33	Added rv32i config for regression of wally32periph	2022-09-07 09:37:59 -07:00
Ross Thompson	5a0cda9860	Merge branch 'multimanager' into main	2022-09-07 10:54:27 -05:00
David Harris	19e449b83d	Fixed regression for divsqrt radix2	2022-09-07 06:12:23 -07:00
Ross Thompson	c87268baf1	Modified ram_ahb to work with different latencies.	2022-09-04 14:46:15 -05:00
David Harris	5e26bcced1	Fixed lint errors in square root and improved waveforms in testfloat	2022-09-01 15:49:13 -07:00
Ross Thompson	f2f1169a04	Renamed AHBCachebusdp to abhcacheinterface.	2022-08-31 14:12:19 -05:00
Ross Thompson	f3d611c686	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-31 11:38:29 -05:00
Ross Thompson	5409501ca6	Maybe fixed it?	2022-08-30 18:08:34 -05:00
Ross Thompson	cce3fdd0e3	Updates to wave file.	2022-08-30 17:34:36 -05:00
Ross Thompson	8b9f30c91a	more progress.	2022-08-30 17:32:32 -05:00
Ross Thompson	fab3a2b791	Temporary commit.	2022-08-30 15:40:42 -05:00
Ross Thompson	315f662eb9	More progress.	2022-08-30 15:27:19 -05:00
Ross Thompson	637d60b64c	Progress.	2022-08-30 14:17:00 -05:00
David Harris	e1760dde55	Fixed checking termination in testfloat testbench	2022-08-30 10:55:21 -07:00
David Harris	7d4e85bf21	Separated out radix 2 and radix 4 stages into different modules	2022-08-29 04:26:14 -07:00
David Harris	2788022c22	renamed srt to fdivsqrt	2022-08-29 04:04:05 -07:00
David Harris	f2517f8290	Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.	2022-08-27 20:31:09 -07:00
David Harris	60b673cafd	Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus	2022-08-27 05:31:56 -07:00
David Harris	37f0b52520	Fixed address decoder hanging buildroot	2022-08-26 22:01:25 -07:00
Ross Thompson	3b612d6201	Possible fixes for earily messup of rv32ic and rv64ic configs.	2022-08-25 14:42:08 -05:00
Ross Thompson	b0aea77b20	Added generate around uncore.	2022-08-25 10:35:24 -05:00
Ross Thompson	01a7718471	Added generate around ebu.	2022-08-25 09:24:13 -05:00
Ross Thompson	d10edfa5e0	No longer need wally-pipelined-fpga.do.	2022-08-24 18:10:45 -05:00
Ross Thompson	fc22e807e2	Merged testbench-fpga into testbench. ... Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.	2022-08-24 17:52:25 -05:00
Ross Thompson	517c0f6c35	Changed signal names.	2022-08-17 16:12:04 -05:00
Katherine Parry	cb0c1b7488	radix-2 1 copy passes testfloat	2022-08-06 22:54:05 +00:00
David Harris	7e5b78f240	plic-s debug	2022-08-03 12:33:09 +00:00
Ross Thompson	413a9bf58b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-01 22:09:11 -05:00
David Harris	257107f908	Partitioned fma into separate files	2022-08-01 18:07:38 +00:00
Ross Thompson	1ee613ae6c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-31 12:48:51 -05:00
David Harris	2d7f4b133c	More work toward riscof tests	2022-07-26 06:19:13 -07:00
David Harris	416f5edfe0	More riscof makefile tuning	2022-07-25 21:15:56 +00:00
David Harris	7f7b3359b0	Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings	2022-07-25 20:50:38 +00:00
Ross Thompson	719b00e338	Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.	2022-07-24 01:20:29 -05:00
Ross Thompson	69d520a7eb	Removed replay from the config files.	2022-07-24 00:34:11 -05:00
Ross Thompson	f3cf46d633	Added more i-cache signals to wave file.	2022-07-24 00:24:13 -05:00
Ross Thompson	8193946996	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-23 08:41:59 -05:00
Ross Thompson	abc79c6c8e	Possible improvement to cache which removes the cpu_busy states.	2022-07-22 23:20:37 -05:00
Daniel Torres	d0aaae26fe	fixed wally rv32e tests, updated regression makefile to new testflow	2022-07-22 17:09:46 -07:00
Katherine Parry	b3d932cd61	divider sizes reworked to match book	2022-07-22 22:02:04 +00:00
Katherine Parry	fbe8bb2298	radix-4 division integrated into srt - not tested	2022-07-21 19:38:06 +00:00