Rose Thompson
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b1a711ae0f
|
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
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2024-07-24 12:47:50 -05:00 |
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Rose Thompson
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27f89fcdbd
|
Updated verilog-ethernet to remove all verilator warnings or at least suppress them.
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2024-07-24 10:13:03 -05:00 |
|
Jordan Carlin
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bb5c9f9ead
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Switch to logger function and fix exit codes
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2024-07-23 23:42:03 -07:00 |
|
Jordan Carlin
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d08deddcc4
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Update logging grep
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2024-07-23 23:40:42 -07:00 |
|
Jordan Carlin
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121ee51503
|
Fix logging
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2024-07-23 23:40:03 -07:00 |
|
Jordan Carlin
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47452ddaaa
|
Remove hardcoded /opt/riscv
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2024-07-23 23:29:45 -07:00 |
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Rose Thompson
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9404a339ee
|
Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings.
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2024-07-23 17:44:37 -05:00 |
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Rose Thompson
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6c212ebf0e
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Changes are confirmed to work on the FPGA.
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2024-07-23 17:39:38 -05:00 |
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Jacob Pease
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f1cc7dd5a3
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Fixed verilog bugs.
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2024-07-23 17:26:39 -05:00 |
|
Jacob Pease
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dcb2edf888
|
Fixed syntax bugs. inline functions are now static and in the spi.h header.
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2024-07-23 17:00:32 -05:00 |
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Rose Thompson
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e8e71ad643
|
Code cleanup.
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2024-07-23 16:35:05 -05:00 |
|
Jacob Pease
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5f0addd69a
|
Initial pass on SPI based bootloader code finished.
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2024-07-23 16:33:49 -05:00 |
|
Jacob Pease
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a8b9e7776b
|
Added some minor error checking to gpt.c.
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2024-07-23 16:32:52 -05:00 |
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Jacob Pease
|
ab00ea5a5c
|
Added sd_read64 to help with block reads and crc checking.
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2024-07-23 16:32:29 -05:00 |
|
Rose Thompson
|
57ea39d685
|
Fixed rvvi csr counting.
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2024-07-23 16:22:23 -05:00 |
|
Rose Thompson
|
54e0289608
|
Fixed bugs in the rvvi synth logic which encoded csr instructions.
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2024-07-23 16:16:11 -05:00 |
|
Jacob Pease
|
57eeba5c8c
|
Progress made on implementing new disk read function.
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2024-07-23 15:47:23 -05:00 |
|
Jacob Pease
|
9ccb0eb027
|
Removed references to card_type.
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2024-07-23 15:46:18 -05:00 |
|
Jacob Pease
|
d9afaade03
|
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
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2024-07-23 14:18:50 -05:00 |
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Jacob Pease
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bf65cd2817
|
Added uart print functions and the Wally banner. SD card can now be initialized. Removed old code from boot.c
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2024-07-23 14:18:42 -05:00 |
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Rose Thompson
|
1eff86b7ae
|
Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet.
|
2024-07-23 13:18:03 -05:00 |
|
Rose Thompson
|
c463201d68
|
Moved all rvvi files to rvvi directory.
|
2024-07-23 13:03:21 -05:00 |
|
Rose Thompson
|
825dbefcb2
|
Fixed bus width error. Have to check this FPGA to make sure this didn't break anything.
|
2024-07-23 12:26:03 -05:00 |
|
Rose Thompson
|
bb74a0f96b
|
Resolved more lint errors in the rvvi synthesized hardware.
|
2024-07-23 12:23:04 -05:00 |
|
Rose Thompson
|
42f2469ea7
|
Merge pull request #891 from davidharrishmc/dev
Increased covergen.py functional coverage to 87.6%
|
2024-07-23 09:34:13 -05:00 |
|
David Harris
|
a4a0a10879
|
Increased covergen.py functional coverage to 87.6%
|
2024-07-23 04:38:13 -07:00 |
|
Jordan Carlin
|
36ffeb2dca
|
Fix minimum scipy version for Ubuntu20.04
|
2024-07-23 01:03:10 -07:00 |
|
Jordan Carlin
|
d096e2e4f8
|
Fix python version for Ubuntu 20.04
|
2024-07-23 00:16:27 -07:00 |
|
Jordan Carlin
|
e4c38dd766
|
Add logs and reduce console output
|
2024-07-22 23:13:38 -07:00 |
|
Jordan Carlin
|
d045fb6662
|
Update python versions
|
2024-07-22 23:12:48 -07:00 |
|
Jordan Carlin
|
16dd728ed6
|
Use requirements file for pip packages
|
2024-07-22 23:12:27 -07:00 |
|
Jordan Carlin
|
4e8cc68d3e
|
Add DEBIAN_FRONTEND=noninteractive to apt
|
2024-07-22 23:11:33 -07:00 |
|
Jordan Carlin
|
8c8e1a3fef
|
Update section header function usage
|
2024-07-22 23:10:45 -07:00 |
|
Rose Thompson
|
94a1ce32e7
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2024-07-22 17:48:34 -05:00 |
|
Rose Thompson
|
8ca565ed53
|
Updated for a better ILA rvvi debugger.
|
2024-07-22 17:44:04 -05:00 |
|
Jacob Pease
|
b05052311f
|
Added sd_cmd and utility SPI functions.
|
2024-07-22 16:57:04 -05:00 |
|
Rose Thompson
|
121342f4cc
|
Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
|
2024-07-22 16:12:06 -05:00 |
|
Jacob Pease
|
6a9141e3be
|
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
|
2024-07-22 13:06:05 -05:00 |
|
Jacob Pease
|
cec39fd3aa
|
Added new SDC clock constraint.
|
2024-07-22 13:05:16 -05:00 |
|
Jacob Pease
|
a506d76149
|
Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP.
|
2024-07-22 12:36:39 -05:00 |
|
Rose Thompson
|
00c30239bf
|
Cleaned up rvvisynth.sv
|
2024-07-22 12:22:41 -05:00 |
|
Rose Thompson
|
556c210e76
|
Added option to use rvvi ila
|
2024-07-22 12:19:37 -05:00 |
|
Rose Thompson
|
7223b15134
|
Merge branch 'rvvi'
|
2024-07-22 12:01:01 -05:00 |
|
Rose Thompson
|
32903a38f5
|
Merge pull request #890 from davidharrishmc/dev
Fixed argument name in regression-wally
|
2024-07-22 12:00:25 -05:00 |
|
David Harris
|
4c46315907
|
Fixed argument name in regression-wally
|
2024-07-22 09:19:56 -07:00 |
|
Rose Thompson
|
844bc01c0a
|
Merge pull request #889 from davidharrishmc/dev
Functional coverage improvements, fix WARL bug on MTVEC/STVEC
|
2024-07-22 10:59:16 -05:00 |
|
David Harris
|
040b359813
|
Added more RV64I coverage generation
|
2024-07-22 08:52:19 -07:00 |
|
Rose Thompson
|
24609f0b7f
|
Now have configurations to switch between supporting RVVI over ethernet.
|
2024-07-22 10:51:13 -05:00 |
|
David Harris
|
757cc8a5f7
|
Added QuestaFunctCoverage to merge functional coverage reports
|
2024-07-22 08:49:54 -07:00 |
|
David Harris
|
c4400dfeb0
|
Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode
|
2024-07-22 08:45:08 -07:00 |
|