97 Commits

Author	SHA1	Message	Date
Ross Thompson	cec7625d91	Added comment about needed fix to misaligned fault.	2022-03-22 16:52:07 -05:00
Ross Thompson	2a8a1cd191	Minor cleanup to interlockfsm.	2022-03-08 23:38:58 -06:00
Ross Thompson	ed32801cc1	Comments.	2022-03-08 18:05:25 -06:00
Ross Thompson	534fd70f76	Marked signals for name changes.	2022-03-08 17:41:02 -06:00
Ross Thompson	acd60218b8	Removed unused signal.	2022-03-08 16:58:26 -06:00
Ross Thompson	60e6c1ffa7	Moved cacheable signal into cache.	2022-03-08 16:34:02 -06:00
David Harris	48705457d5	LSU/Cache code review notes	2022-03-04 00:07:31 +00:00
Ross Thompson	62e1a97287	Added generates to pcnextf muxes for privileged and caches.	2022-02-22 22:45:00 -06:00
Ross Thompson	6a52f95cc8	Minor busdp cleanup.	2022-02-22 17:28:26 -06:00
Ross Thompson	90be3d4360	Clarified interlockfsm.	2022-02-22 11:31:28 -06:00
Ross Thompson	3a29504279	Added some clearity to lsuvirtmem.sv.	2022-02-21 17:20:58 -06:00
Ross Thompson	2f711fb642	Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.	2022-02-21 16:54:38 -06:00
Ross Thompson	0c65ea96d8	Cleaned up names in lsuvirtmem.	2022-02-21 16:44:30 -06:00
Ross Thompson	56fc6d0d7c	Minor cleanup of lsu.	2022-02-21 12:46:06 -06:00
Ross Thompson	f48b12b089	Moved mux into lsuvirtmem.	2022-02-21 09:31:29 -06:00
Ross Thompson	ae06785b9f	Minor changes to LSU.	2022-02-19 14:38:17 -06:00
Ross Thompson	6cd9d84e7f	New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.	2022-02-17 17:19:41 -06:00
Ross Thompson	0eec096474	Rough implementation passing regression test with hptw atomic writes to memory.	2022-02-17 14:46:11 -06:00
Ross Thompson	2fc7dc3e57	Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.	2022-02-17 10:04:18 -06:00
Ross Thompson	62f5f1e622	Broken state. address translation not working after changes to hptw to support atomic updates to PT.	2022-02-16 23:37:36 -06:00
Ross Thompson	c9e33208e3	Moved a few muxes around after sww changes.	2022-02-16 15:43:03 -06:00
Ross Thompson	71ed49bf2b	cleanup of signal names.	2022-02-16 15:29:08 -06:00
Ross Thompson	27042f028e	Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.	2022-02-16 15:22:19 -06:00
Ross Thompson	1e7e59bdbd	Changed names of signals in cache.	2022-02-13 15:06:18 -06:00
Ross Thompson	c8e6884926	Fixed bug. ... It was possible for DTLBMissM to prevent a dcache flush.	2022-02-11 14:00:01 -06:00
David Harris	15fb7fee60	Cleaned up synthesis warnings	2022-02-11 01:15:16 +00:00
Ross Thompson	411997010b	Replacement policy cleanup.	2022-02-10 11:40:10 -06:00
Ross Thompson	382d5fab0f	Cleanup.	2022-02-10 11:27:15 -06:00
Ross Thompson	3a0af5d9e9	Cleanup + critical path optimizations.	2022-02-10 11:11:16 -06:00
Ross Thompson	911ee36b22	Removed all possilbe paths to PreSelAdr from TrapM.	2022-02-09 19:20:10 -06:00
Ross Thompson	01126535db	Annotated the final changes required to move sram address off the critial path.	2022-02-08 18:17:31 -06:00
Ross Thompson	3cd067ac6a	Finished merge.	2022-02-08 11:36:24 -06:00
David Harris	096242a6d8	Merged TIM and regular testbenches. RV32e now working and back in regression.	2022-02-08 12:18:13 +00:00
Ross Thompson	1766c0f5ba	Removed unused ports from caches and buses.	2022-02-04 22:52:51 -06:00
Ross Thompson	dce4f8a0e5	Cleanup.	2022-02-04 22:40:51 -06:00
Ross Thompson	53551ab533	Moved the hwdata mux back into the busdp.	2022-02-04 22:39:13 -06:00
Ross Thompson	34cf77797a	Merged together the two sub cache line read muxes. ... One mux was used for loads and the other for eviction.	2022-02-04 22:30:04 -06:00
Ross Thompson	c846368537	Moved the sub cache line read logic to lsu/ifu.	2022-02-04 20:42:53 -06:00
David Harris	e92461159d	cache cleanup	2022-02-03 15:36:11 +00:00
David Harris	9e0055cbb9	More config file cleanup; 32ic tests broken	2022-02-03 01:08:34 +00:00
David Harris	bdf1a8ba73	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
David Harris	c12407ba6a	Removed Busybear dependencies	2022-02-02 20:28:21 +00:00
Ross Thompson	a04aa283cb	partial ifu cleanup.	2022-01-31 16:08:53 -06:00
Ross Thompson	b05abc1795	cleanup.	2022-01-31 13:29:04 -06:00
Ross Thompson	d2ab17e1af	Repaired linux-wave.do	2022-01-31 12:54:18 -06:00
Ross Thompson	3475e142a5	Repaired wavefile and fixed modelsim warning.	2022-01-31 12:34:17 -06:00
Ross Thompson	fa8914a830	Cleanup busdp.	2022-01-31 12:17:07 -06:00
Ross Thompson	7c3d6bbdb4	Moved lsu virtual memory logic into separate module.	2022-01-31 11:56:03 -06:00
Ross Thompson	e35a8299ec	Encapsulated dtim.	2022-01-31 11:23:55 -06:00
Ross Thompson	dbe40856a2	Removed unused signals in the LSU.	2022-01-31 10:35:35 -06:00