19 Commits

Author	SHA1	Message	Date
Ross Thompson	7f0ba87231	Updated comments in uart.	2024-06-19 13:51:30 -07:00
David Harris	c1fd7a9589	Removed unused signals	2024-06-18 07:28:52 -07:00
David Harris	7509e856df	Removed asynchronous reset causing lint issue in peripherals	2024-06-18 05:49:12 -07:00
David Harris	4a4bbdfc43	More code cleanup	2024-06-14 09:50:07 -07:00
David Harris	8f09240e6c	Simplified outdated documentation pointers	2024-06-14 03:42:15 -07:00
David Harris	0419b5484a	parameterized register names in peripherals	2024-04-21 07:43:01 -07:00
Kunlin Han	22b59138f0	Remove all #delay from non-testbench.	2024-03-16 11:20:32 -07:00
Kunlin Han	8c67a76912	Remove all #delay from non-testbench.	2024-03-13 10:31:40 -07:00
David Harris	e0eb91f795	Changed always @(posedge clk) to always_ff @(posedge clk) where it was omitted in several places	2024-03-06 11:02:04 -08:00
David Harris	45e2317636	Added Wally github address to header comments	2024-01-29 05:38:11 -08:00
Ross Thompson	bdc5656ef3	Added comment to uart LCR to check reset value after updating FPGA.	2023-06-15 15:39:51 -05:00
David Harris	d3aebc00d4	Fixed UART merge conflict	2023-06-15 11:36:37 -07:00
Harshini Srinath	59178a2e56	Update uartPC16550D.sv ... Program clean up	2023-06-15 10:20:29 -07:00
David Harris	9da4005a1e	Removed *** from UART code	2023-06-14 08:47:01 -07:00
David Harris	5a2bcb917f	Removed QEMU from UART	2023-06-14 08:39:01 -07:00
Ross Thompson	3cc85349b5	Uncore is now parameterized.	2023-05-26 16:24:12 -05:00
Ross Thompson	ca4b058373	Modified plic and uart to remove async reset. This removes vivado critical warning.	2023-03-24 20:37:48 -05:00
Ross Thompson	46b1bca4fc	Fixed all tap/space issue in RTL.	2023-03-24 17:32:25 -05:00
David Harris	78eb90715c	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00