117 Commits

Author	SHA1	Message	Date
Ross Thompson	403434580d	Fixed the uart transmit fifo overrun bug.	2022-10-26 14:48:09 -05:00
Jacob Pease	160ca366c8	Added PLIC signals for debugging on FPGA.	2022-10-25 13:57:09 -05:00
Ross Thompson	9ba487c323	Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.	2022-10-24 15:38:39 -05:00
Ross Thompson	7244ca1e7b	Bit width error.	2022-10-24 13:48:47 -05:00
Jacob Pease	b1170ec7a2	Extended rxfifotimeout count to actually be 4 characters long.	2022-10-20 17:35:49 -05:00
Ross Thompson	92accfb1a6	Updated uart settings and fpga wave config.	2022-10-18 15:05:33 -05:00
Ross Thompson	d81af3bca8	Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore.	2022-09-29 11:54:03 -05:00
Ross Thompson	66c45949b5	Renamed brom1p1r to rom1p1r. ... removed used file bram2p1r1w.sv.	2022-09-21 12:31:20 -05:00
Ross Thompson	ac864a6ca3	Merged together bram1p1rw with sram1p1rw as sram1p1rw. ... Fixed a major issue with the real SRAM implemenation.	2022-09-21 12:20:00 -05:00
Ross Thompson	426ec6222b	Added chip enables to sram.	2022-09-20 10:49:14 -05:00
Jacob Pease	1e7bbe1a87	Fixed rxfifotimeout restarting for every new character, even when already high.	2022-09-19 18:00:30 -05:00
Ross Thompson	68a200d728	Added generate around the longer latency version of the ram_ahb.sv	2022-09-06 09:21:03 -05:00
Ross Thompson	2554f96662	Cleaned up hacks to ram.	2022-09-04 14:52:40 -05:00
Ross Thompson	c87268baf1	Modified ram_ahb to work with different latencies.	2022-09-04 14:46:15 -05:00
Ross Thompson	f9daa7f6b9	Progress towards fixing the select HREADY muxing in uncore.	2022-09-04 13:07:49 -05:00
Ross Thompson	4d60d9a840	Fixed up FPGA constraints. ... Added back in the fpga boot rom preload.	2022-09-02 13:54:35 -05:00
Ross Thompson	122c88ee46	Created two new pma regions for dtim and irom.	2022-08-28 13:50:50 -05:00
Ross Thompson	5e63af5887	Reordered the adrdecs.	2022-08-28 13:38:57 -05:00
David Harris	f2517f8290	Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.	2022-08-27 20:31:09 -07:00
David Harris	f0b4f69b65	Added IROM and DTIM decoding to adrdecs	2022-08-26 20:45:43 -07:00
David Harris	902d2067ba	Removed delayed AHB signals from top level	2022-08-25 15:34:14 -07:00
David Harris	302a7fa294	Extended HADDR to PA_BITS	2022-08-25 13:11:36 -07:00
Ross Thompson	ad485fe591	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-25 09:03:34 -05:00
Ross Thompson	701324eeb8	Updated ila signals. ... Improve fpga wave config. added back in the fpga preload.	2022-08-25 09:03:29 -05:00
David Harris	562be633ab	Stripped write capaibilty out of rom_ahb	2022-08-24 17:23:08 -07:00
David Harris	a131e1f17a	Added ROM module and moved memories into generic/mem	2022-08-24 17:03:22 -07:00
David Harris	6785644fb8	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-24 16:30:28 -07:00
David Harris	b21b91234b	Ram cleanup	2022-08-24 16:30:25 -07:00
Ross Thompson	769af32f2a	Renamed RAM to UNCORE_RAM.	2022-08-24 18:09:07 -05:00
Ross Thompson	fc22e807e2	Merged testbench-fpga into testbench. ... Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.	2022-08-24 17:52:25 -05:00
David Harris	93d7d7179e	Added parity and stop bit tests to UART	2022-07-28 04:35:51 +00:00
slmnemo	ca4511b6dc	Fixed UART FIFO bugs and added FIFO tests	2022-07-22 17:13:19 -07:00
David Harris	d22587090b	Reset MSR on read	2022-07-22 04:29:27 +00:00
slmnemo	3d2c6683d8	Fixed UART bug related to parity and MSR/LSR	2022-07-21 20:35:46 -07:00
David Harris	622773343f	restored intPending logic to be sticky for PLIC	2022-07-16 17:43:31 -07:00
David Harris	5ae88dbef0	Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc	2022-07-08 09:09:02 +00:00
David Harris	96cc66d151	Adjusting byte writes to RAM	2022-07-08 08:45:21 +00:00
David Harris	234175f236	Removed unused swbytemask from CLINT	2022-07-08 08:43:24 +00:00
David Harris	76302a8599	PLIC and UART passing tests on APB	2022-07-06 13:26:14 +00:00
David Harris	72e216d053	APB CLINT passing regression	2022-07-05 15:51:35 +00:00
David Harris	5f5ad77d4a	Modified uncore to use AHB bridge to GPIO	2022-07-05 05:02:21 +00:00
David Harris	c8ac05ba7b	AHB bridge for gpio	2022-07-05 05:01:59 +00:00
David Harris	1a356312b2	Added comments to PLIC about likely bug	2022-07-05 05:00:29 +00:00
David Harris	44216b3967	Fixed typo in clint	2022-06-23 21:27:46 +00:00
David Harris	d969edeb99	Reset mtimecmp in clint	2022-06-23 21:20:55 +00:00
David Harris	802bfd74fb	Cleanup on RAM module	2022-06-13 19:37:43 +00:00
David Harris	3c44b5842b	Typo in gpio reset	2022-06-13 19:37:05 +00:00
David Harris	09d72a33c5	Fixed XOR logic in GPIO	2022-06-13 19:26:03 +00:00
slmnemo	cc8acd947d	Fixed lint error	2022-06-09 17:22:04 -07:00
David Harris	c1a40a15dd	New RAM for further testing	2022-06-09 23:50:43 +00:00