David Harris
a5a922d048
Removed unnecessary configuration conditions from subwordread sign extension/NaN boxing
2022-10-10 07:12:37 -07:00
cturek
c72e2e5d49
Added integer inputs and flags to divsqrt
2022-09-29 23:08:27 +00:00
Ross Thompson
638e506d0b
Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
2022-09-28 17:39:51 -05:00
Ross Thompson
f24b0feeed
renamed ahbmulticontroller to ebu.
2022-09-26 14:37:18 -05:00
Ross Thompson
cc1ba84637
Found the ahb burst bug.
...
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests. It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads. The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads. In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
2022-09-17 20:30:01 -05:00
Ross Thompson
db56a326c9
renamed multimanager to multicontroller.
2022-09-14 14:03:37 -05:00
Ross Thompson
1c248e5164
Removed old signals.
2022-08-31 09:50:39 -05:00
Ross Thompson
5eb1fff27d
Have a rough working multi manager!
2022-08-29 17:11:27 -05:00
Ross Thompson
4f40bd07c3
Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu.
2022-08-29 17:04:53 -05:00
Ross Thompson
4d7b905806
Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager.
2022-08-29 13:01:24 -05:00
David Harris
352bf88ac0
FIxed wallypipelinedsoc merge conflict
2022-08-25 15:36:47 -07:00
David Harris
b96942e84c
Removed delayed AHB signals from top level
2022-08-25 15:34:14 -07:00
Ross Thompson
109bcd470e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-25 16:01:02 -05:00
David Harris
6222e15946
Extended HADDR to PA_BITS
2022-08-25 13:11:36 -07:00
Ross Thompson
502eb0f5d1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-25 14:40:52 -05:00
David Harris
5dc4fb757a
Continued busdp/ebu simplification
2022-08-25 10:20:02 -07:00
David Harris
24ce72f0a2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-25 09:52:49 -07:00
David Harris
89860588b8
Renamed AHB signals coming out of LSU to LSH_<AHBNAME>
2022-08-25 09:52:08 -07:00
Ross Thompson
bd9401179d
BROKEN. Don't use this commit.
...
Issue running cacheless with bus.
2022-08-25 11:02:46 -05:00
Ross Thompson
5cc4f1f1cd
Added generate around uncore.
2022-08-25 10:35:24 -05:00
Ross Thompson
1e1646da90
Added generate around ebu.
2022-08-25 09:24:13 -05:00
David Harris
8d48ff4e63
Fixed FPU-IEU forwarding stall
2022-08-23 14:14:41 -07:00
David Harris
113258a0d0
Cleaned up fcvt selection control to IEU and FPUIllegalInst signals
2022-08-23 12:17:19 -07:00
David Harris
24a05c35d9
Renamed signals for LSU - FPU interface
2022-08-22 13:47:56 -07:00
David Harris
7151befd04
Removed FStore2 and simplified HPTW
2022-08-22 13:29:54 -07:00
Ross Thompson
a049f456e8
Removed logic from Verilog wrapper.
2022-08-21 14:07:43 -05:00
Ross Thompson
5d9dab6149
pulled swbbytemask out of subword write.
2022-08-01 20:48:45 -05:00
Katherine Parry
2ada8a8bc1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-07-12 22:37:20 +00:00
Katherine Parry
ca4fe08fd9
renamed FLoad2 to FStore2
2022-07-09 00:26:45 +00:00
David Harris
381f3298d8
Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc
2022-07-08 09:09:02 +00:00
David Harris
2f342c430e
fixing port errors
2022-07-07 21:57:10 +00:00
David Harris
d73645944f
APB CLINT passing regression
2022-07-05 15:51:35 +00:00
Katherine Parry
6baded9121
added rv32 double precision stores - untested
2022-06-28 21:33:31 +00:00
Katherine Parry
254ebf478e
added fld in rv32 - needs testing
2022-06-20 22:53:13 +00:00
Katherine Parry
31fd8772cf
postprocessing unit created and passing all tests
2022-06-13 22:47:51 +00:00
slmnemo
054cf5f7b0
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
2022-06-08 15:03:15 -07:00
slmnemo
284e0395a0
Merge branch 'main' into cacheburstmode
2022-06-08 02:21:33 +00:00
slmnemo
2d76953d42
Added lock signal to ensure AHB speaks with the right bus
2022-06-08 02:19:21 +00:00
slmnemo
73e0c1c07f
Reworked bus to handle burst interfacing
2022-06-07 11:22:53 +00:00
David Harris
1d8bc2dc1b
Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit
2022-06-02 09:37:59 -07:00
David Harris
c7ec9282fe
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
2022-06-02 14:18:55 +00:00
slmnemo
847c7930c4
added LSUBurstDone signal to signal when a burst has finished
2022-05-26 16:29:13 -07:00
slmnemo
08430a1e85
added burst size signals to the IFU, EBU, LSU, and busdp
2022-05-25 18:02:50 -07:00
David Harris
ce24c080d5
More unused signal cleanup
2022-05-12 15:26:08 +00:00
David Harris
5670f77de2
More unused signal cleanup
2022-05-12 15:21:09 +00:00
David Harris
e2e63ca9a8
Clean up unused signals
2022-05-12 14:49:58 +00:00
David Harris
8166fd772e
Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt
2022-05-11 15:08:33 +00:00
David Harris
137b411bea
Removed M suffix from interrupts because they are generated asynchronously to pipeline
2022-05-11 14:41:55 +00:00
David Harris
4f1b0fdc64
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
2022-05-08 06:46:35 +00:00
David Harris
a516f89f22
WFI terminates when an interrupt is pending even if interrupts are globally disabled
2022-05-08 04:30:46 +00:00
